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mos integrated circuit m m m m pd30111 v r 4111 tm 64-/32-bit microprocessor document no. u13211ej2v0ds00 (2nd edition) date published august 1999 n cp(k) printed in japan data sheet the mark shows major revised points. description the m pd30111 (v r 4111) is one of nec's v r series risc (reduced instruction set computer) microprocessors and is a high-performance 64-/32-bit microprocessor employing the mips tm risc architecture. the v r 4111 uses the high-performance, super power-saving v r 4110 tm as the cpu core, and has many peripheral functions such as a dma controller, software modem interface, serial interface, keyboard interface, irda interface, touch panel interface, real-time clock, a/d converter, and d/a converter. configured with these functions, the v r 4111 is suitable for high-speed battery-driven portable information systems. the external memory bus width can be selected from 32 bits and 16 bits, realizing high-speed data transfer. detailed function descriptions are provided in the following users manual. be sure to read it before designing. v r 4111 user's manual (u13137e) features ? employs 64-bit mips architecture ? conforms to mips iii instruction set (deleting fpu, ? dram interface and mask rom interface to support flash memory ll, lld, sc, and scd instructions) ? keyboard interface and touch panel interface ? optimized 5-stage pipeline ? 4-channel dma controller ? supports mips16 instruction set ? serial interface (ns16550 compatible) ? irda interface for infrared communication ? supports high-speed product-sum operation instructions ? software modem interface ? a/d and d/a converters to support digital voice i/o ? supports four types of operating modes, enabling more effective power-consumption management ? supports isa bus subset ? internal maximum operating frequency: 70 mhz ? on-chip clock generator ? power supply voltage: internal 2.3 to 2.7 v, external 3.0 to 3.6 v ? address space physical: 32 bits virtual: 40 bits integrates 32 double entry tlbs ? package: 224-pin fine-pitch fbga ? high-capacity instruction/data separated cache memories instruction: 16 kbytes data: 8 kbytes applications battery-driven portable information systems embedded controllers, etc. ordering information part number package internal maximum operating frequency m pd30111s1-70-3c 224-pin fine-pitch bga (16 16 mm) 70 mhz the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local nec representative for availability and additional information.
data sheet u13211ej2v0ds00 2 m m m m pd30111 pin configuration 224-pin fine pitch bga (16 16 mm) m pd30111s1-70-3c index mark vutrpnmlkjhgfedcba abcdefghjklmnprtuv 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 bottom view top view
data sheet u13211ej2v0ds00 3 m m m m pd30111 pin no. power supply pin name pin no. power supply pin name pin no. power supply pin name a1 3.3 v v dd 3 c15 3.3 v rts#/clksel1 h15 3.3 v gnd3 a2 3.3 v shb# c16 3.3 v gnd3 h16 3.3 v kport6 a3 3.3 v busclk c17 3.3 v ilcsense h17 3.3 v kport4 a4 3.3 v hldack# c18 3.3 v aferst# h18 2.5 v v dd 2 a5 3.3 v iochrdy d1 3.3 v data5 j1 3.3 v data20/gpio20 a6 3.3 v memw# d2 3.3 v data3 j2 3.3 v data17/gplo17 a7 3.3 v add23 d3 3.3 v data6 j3 3.3 v data22/gplo22 a8 3.3 v v dd 3 d4 3.3 v gnd3 j4 3.3 v data19/gpio19 a9 3.3 v add18 d5 3.3 v memcs16# j15 3.3 v kscan9/gpio41 a10 3.3 v add15 d6 3.3 v add25 j16 3.3 v v dd 3 a11 3.3 v add8 d7 3.3 v gnd3 j17 2.5 v gnd2 a12 3.3 v add7 d8 3.3 v add19 j18 3.3 v kscan11/gpio43 a13 2.5 v v dd 2 d9 3.3 v add16 k1 3.3 v data23/gpio23 a14 3.3 v dcd#/gpio15 d10 3.3 v add14 k2 3.3 v data26/gpio26 a15 3.3 v txd/clksel2 d11 3.3 v v dd 3 k3 3.3 v data25/gpio25 a16 3.3 v irdout# d12 3.3 v gnd3 k4 3.3 v data21/gpio21 a17 3.3 v iring d13 3.3 v add4 k15 3.3 v kscan7/gpio39 a18 3.3 v v dd 3 d14 3.3 v cts# k16 3.3 v kscan10/gpio42 b1 3.3 v data1 d15 3.3 v gnd3 k17 3.3 v kscan5/gpio37 b2 3.3 v ior# d16 3.3 v gnd3 k18 3.3 v kscan8/gpio40 b3 3.3 v iow# d17 3.3 v sdi l1 3.3 v data27/gpio27 b4 3.3 v ledout# d18 3.3 v sdo l2 3.3 v data31/gpio31 b5 3.3 v firclk e1 3.3 v data9 l3 3.3 v data29/gpio29 b6 3.3 v hldrq# e2 3.3 v data4 l4 3.3 v data24/gpio24 b7 3.3 v zws# e3 3.3 v data7 l15 3.3 v kscan3/gpio35 b8 3.3 v add24 e4 3.3 v data10 l16 3.3 v kscan6/gpio38 b9 3.3 v add21 e15 3.3 v opd# l17 3.3 v kscan0/gpio32 b10 3.3 v add12 e16 3.3 v hspsclk l18 3.3 v kscan4/gpio36 b11 3.3 v add6 e17 3.3 v fs m1 3.3 v data30/gpio30 b12 2.5 v gnd2 e18 3.3 v hc0 m2 3.3 v v dd 3 b13 3.3 v dsr# f1 3.3 v data13 m3 3.3 v gnd3 b14 3.3 v irdin f2 3.3 v data8 m4 3.3 v data28/gpio28 b15 3.3 v firdin#/sel f3 3.3 v data11 m15 3.3 v kscan2/gpio34 b16 3.3 v battinh/battint# f4 3.3 v data14 m16 3.3 v mips16en b17 3.3 v offhook f15 3.3 v kport3 m17 3.3 v gnd3 b18 3.3 v mute f16 3.3 v hspmclk m18 3.3 v kscan1/gpio33 c1 3.3 v data2 f17 3.3 v telcon n1 2.5 v v dd 2 c2 3.3 v data0 f18 3.3 v kport1 n2 3.3 v add3 c3 3.3 v gnd3 g1 2.5 v v dd 2 n3 3.3 v add10 c4 3.3 v gnd3 g2 3.3 v data12 n4 3.3 v gnd2 c5 3.3 v gnd3 g3 3.3 v data15 n15 3.3 v gnd3 c6 3.3 v iocs16# g4 3.3 v gnd3 n16 3.3 v v dd 3 c7 3.3 v memr# g15 3.3 v kport7 n17 2.5 v v dd p c8 3.3 v add22 g16 3.3 v kport2 n18 3.3 v gnd3 c9 3.3 v add20 g17 3.3 v kport0 p1 3.3 v add9 c10 3.3 v add17 g18 3.3 v kport5 p2 3.3 v add0 c11 3.3 v add13 h1 3.3 v data16/gpio16 p3 3.3 v add2 c12 3.3 v add5 h2 2.5 v gnd2 p4 3.3 v add11 c13 3.3 v r x d h3 3.3 v data18/gpio18 p15 2.5 v v dd 2 (v dd pd) c14 3.3 v dtr#/clksel0 h4 3.3 v v dd 3 p16 2.5 v gndp remark # indicates active low.
data sheet u13211ej2v0ds00 4 m m m m pd30111 pin no. power supply pin name pin no. power supply pin name pin no. power supply pin name p17 3.3 v clkx2 t6 3.3 v av dd u13 3.3 v gpio9 p18 2.5 v gnd2 (gndpd) t7 3.3 v lcas# u14 3.3 v gpio6 r1 3.3 v add1 t8 3.3 v romcs2# u15 3.3 v gpio5 r2 3.3 v power t9 3.3 v rd# u16 3.3 v gpio1 r3 3.3 v gnd3 t10 3.3 v wr# u17 3.3 v gpio2 r4 3.3 v gnd3 t11 3.3 v dbus32/gpio48 u18 3.3 v cgnd r5 3.3 v audioin t12 3.3 v ddout/gpio44 v1 3.3 v v dd 3 r6 3.3 v dv dd t13 3.3 v gpio11 v2 3.3 v piugnd r7 3.3 v mras2#/ulcas# t14 3.3 v gpio8 v3 3.3 v tpx0 r8 3.3 v mras1# t15 3.3 v gnd3 v4 3.3 v tpy1 r9 3.3 v romcs1# t16 3.3 v gnd3 v5 3.3 v adin2 r10 3.3 v rstout t17 3.3 v gpio0 v6 3.3 v audioout r11 3.3 v gnd3 t18 3.3 v rtcx1 v7 3.3 v mras3#/uucas# r12 3.3 v gpio49 u1 3.3 v mpower v8 3.3 v mras0# r13 3.3 v ddin/gpio45 u2 3.3 v rtcrst# v9 3.3 v romcs0# r14 3.3 v gpio12 u3 3.3 v agnd v10 3.3 v v dd 3 r15 3.3 v gnd3 u4 3.3 v tpx1 v11 3.3 v lcdcs# r16 3.3 v cv dd u5 3.3 v tpy0 v12 3.3 v dcts#/gpio47 r17 3.3 v rtcx2 u6 3.3 v adin1 v13 3.3 v gpio14 r18 3.3 v clkx1 u7 3.3 v dgnd v14 3.3 v gpio10 t1 3.3 v poweron u8 3.3 v ucas# v15 3.3 v gpio7 t2 3.3 v rstsw# u9 3.3 v romcs3# v16 3.3 v gpio4 t3 3.3 v gnd3 u10 3.3 v ldcrdy v17 3.3 v gpio3 t4 3.3 v piuv dd u11 3.3 v drts#/gpio46 v18 3.3 v v dd 3 t5 3.3 v adin0 u12 3.3 v gpio13 remark # indicates active low.
data sheet u13211ej2v0ds00 5 m m m m pd30111 pin identification add (0:25): address bus kport (0:7): key code data input adin (0:2): general purpose input for a/d kscan (0:11): key scan line aferst#: afe reset lcas#: lower column address strobe agnd: gnd for a/d lcdcs#: lcd chip select audioin: audio input lcdrdy: lcd ready audioout: audio output ledout#: led output av dd :v dd for a/d memcs16#: memory chip select 16 battinh: battery inhibit memr#: memory read battint: battery interrupt request memw#: memory write busclk: system bus clock mips16en: mips16 enable cgnd: gnd for oscillator mpower: main power clksel (0:2): clock select mras(0:3)#: dram row address strobe clkx1: clock x1 mute: mute clkx2: clock x2 offhook: off hook cts#: clear to send opd#: output power down cv dd :v dd for oscillator piugnd: gnd for touch panel interface data (0:31): data bus piuv dd :v dd for touch panel interface dbus32: data bus 32 power: power switch dcd#: data carrier detect poweron: power on state dcts#: debug serial clear to send rd#: read ddin: debug serial data input romcs(0:3)#: rom chip select ddout: debug serial data output rstout: system bus reset output dgnd: gnd for d/a rstsw#: reset switch drts#: debug serial request to send rtcrst#: real-time clock reset dsr#: data set ready rtcx1: real-time clock x1 dtr#: data terminal ready rtcx2: real-time clock x2 dv dd :v dd for d/a rts#: request to send firclk: fir clock rxd: receive data firdin#: fir data input sdi: hsp serial data input fs: frame synchronization sdo: hsp serial data output gnd2, gnd3: ground sel: irda module select gndp, gndpd: ground for pll shb#: system hi-byte enable gpio (0:49): general purpose i/o telcon: telephone control hc0: hardware control 0 tpx (0:1): touch panel x i/o hldack#: hold acknowledge tpy (0:1): touch panel y i/o hldrq#: hold request txd: transmit data hspmclk: hsp codec master clock ucas#: upper column address strobe hspsclk: hsp codec serial clock ilcsense: input loop current sensing ulcas#: lower byte of upper column address strobe iochrdy: i/o channel ready iocs16#: i/o chip select 16 uucas#: upper byte of upper column address strobe ior#: i/o read v dd 2, v dd 3: power supply voltage iow#: i/o write v dd p, v dd pd: v dd for pll irdin: irda data input wr#: write irdout#: irda data output zws#: zero wait state iring: input ring remark # indicates active low.
data sheet u13211ej2v0ds00 6 m m m m pd30111 internal block diagram and example of connection of external blocks lcd panel 480 240 pd16661 m pd16666 m pc card pcmcia /buffer rom/flash memory edo dram osb osb pll hsp rtc dsu icu pmu dcu cmu dmau codec afe v r 4110 cpu core 70 mhz bcu 32.768 khz 18.432 mhz v r 4111 lcd module giu kiu aiu led d/a piu a/d siu fir rs-232c driver ir driver touch panel 48 mhz cpu core internal block diagram virtual address bus internal data bus control (o) control (i) address/data (o) address/data (i) bus interface data cache (8 kbytes) instruction cache (16 kbytes) tlb cp0 cpu clock generator internal clock
data sheet u13211ej2v0ds00 7 m m m m pd30111 contents 1. pin functions............................................................................................................... ................. 10 1.1 pin functions............................................................................................................... ............................ 10 1.2 pin status in specific status ............................................................................................... ................... 18 1.3 types of pin i/o circuits and recommended connection of unused pins ....................................... 21 1.4 pin i/o circuits............................................................................................................ ............................. 24 2. internal blocks........................................................................................................... .................. 25 2.1 v r 4110 cpu core.................................................................................................................. ................... 25 2.2 clock generator............................................................................................................. .......................... 25 2.3 bcu (bus control unit)...................................................................................................... ..................... 25 2.4 rtc (real-time clock unit).................................................................................................. .................. 26 2.5 dsu (deadman's switch unit) ................................................................................................. ............... 26 2.6 icu (interrupt control unit) ................................................................................................ .................... 26 2.7 pmu (power management unit)................................................................................................. ............. 26 2.8 dmaau (direct memory access address unit) ................................................................................... .26 2.9 dcu (direct memory access control unit) ..................................................................................... ...... 26 2.10 cmu (clock mask unit) ...................................................................................................... ..................... 26 2.11 giu (general purpose i/o unit) ............................................................................................. ................. 26 2.12 aiu (audio interface unit)................................................................................................. ...................... 26 2.13 kiu (keyboard interface unit) .............................................................................................. .................. 26 2.14 piu (touch panel interface unit)........................................................................................... ................. 27 2.15 dsiu (debug serial interface unit)......................................................................................... ................ 27 2.16 siu (serial interface unit) ................................................................................................ ....................... 27 2.17 fir (fast irda interface unit) ............................................................................................. .................... 27 2.18 hsp (host signal processing unit).......................................................................................... .............. 27 2.19 led (led unit)............................................................................................................. ............................ 27 3. internal architecture ..................................................................................................... .......... 28 3.1 pipeline.................................................................................................................... ................................. 28 3.2 cpu registers............................................................................................................... ........................... 29 3.3 outline of instruction set.................................................................................................. ...................... 30 3.3.1 mips iii instruction set .................................................................................................. ............... 30 3.3.2 mips16 instruction set .................................................................................................... ............. 32 3.4 system control coprocessor (cp0) ............................................................................................ .......... 33 3.4.1 cp0 registers ............................................................................................................. .................. 33 3.5 data format and addressing .................................................................................................. ............... 35 3.6 virtual storage ............................................................................................................. ............................ 36 3.6.1 virtual address space ..................................................................................................... ............. 36 3.6.2 address translation ....................................................................................................... ............... 39 3.7 physical address space ...................................................................................................... ................... 41 3.7.1 rom address space ......................................................................................................... ........... 42 3.7.2 internal i/o space........................................................................................................ ................. 44 3.7.3 dram address space ........................................................................................................ .......... 45 3.8 cache....................................................................................................................... ................................. 47 3.9 exception processing ........................................................................................................ ..................... 48
data sheet u13211ej2v0ds00 8 m m m m pd30111 4. initialization interface.................................................................................................. ............. 51 4.1 reset function.............................................................................................................. ........................... 51 4.1.1 rtc reset................................................................................................................. .................... 51 4.1.2 rstsw ..................................................................................................................... ................... 52 4.1.3 deadmans sw .............................................................................................................. .............. 53 4.1.4 software shutdown......................................................................................................... .............. 54 4.1.5 haltimer shutdown......................................................................................................... ............ 55 4.2 cpu core registers after reset .............................................................................................. ............... 55 4.3 power-on sequence........................................................................................................... ..................... 56 5. bcu (bus control unit) ....................................................................................................... ....... 58 6. dmaau (dma address unit) ..................................................................................................... ... 59 7. dcu (dma control unit) ....................................................................................................... ...... 60 8. cmu (clock mask unit)........................................................................................................ ........ 61 9. icu (interrupt control unit) ................................................................................................. .61 10. pmu (power management unit) ............................................................................................... 63 10.1 power mode................................................................................................................. ............................. 63 11. rtc (real-time clock unit) .................................................................................................. ..... 65 12. dsu (deadman's sw unit) ..................................................................................................... ....... 66 13. giu (general-purpose i/o unit) .............................................................................................. .67 14. piu (touch panel unit) ...................................................................................................... .......... 68 15. siu (serial interface unit) ................................................................................................. ...... 69 16. aiu (audio interface unit).................................................................................................. ....... 72 17. kiu (keyboard interface unit)............................................................................................... .73 18. dsiu (debug serial interface unit)....................................................................................... 74 19. led (led control unit) ...................................................................................................... ......... 75 20. hsp (modem interface unit) .................................................................................................. ... 76 21. fir (fast irda interface unit).............................................................................................. ..... 77 22. instruction set ............................................................................................................. ............... 78 22.1 mips iii instruction ....................................................................................................... ........................... 78
data sheet u13211ej2v0ds00 9 m m m m pd30111 22.1.1 instruction formats ...................................................................................................... ................. 78 22.1.2 mips iii instruction set list............................................................................................ ................ 78 22.1.3 instruction execution time ............................................................................................... ............. 83 22.2 mips16 instruction ......................................................................................................... ......................... 84 23. electrical specifications................................................................................................... .... 88 24. package drawing ............................................................................................................. ......... 128 25. recommended solering conditions .................................................................................. 129 appendix differences between v r 4111 and v r 4102 ............................................................... 130
data sheet u13211ej2v0ds00 10 m m m m pd30111 1. pin functions remark # indicates active low. 1.1 pin functions (1) system bus interface signals (1/2) signal name i/o function add (0:25) output this is a 26-bit address bus. used to specify addresses of the v r 4111, dram, rom, lcd, and system bus (isa). data (0:15) i/o this is a 16-bit data bus. used to transfer data from the v r 4111 to dram, rom, lcd, and system bus, and vice versa. data (16:31)/ gpio (16:31) i/o this function differs depending on how the dbus32 pin is set. when dbus32 = 1 it is the higher 16 bits of the 32-bit data bus. this bus is used for transmitting and receiving data between the v r 4111 and the dram and rom. when dbus32 = 0 it is a general-purpose i/o (gpio) port. lcdcs# output this is the lcd chip select signal. this signal is active when the v r 4111 is performing lcd access using the add/data bus. rd# output active when the v r 4111 is reading data from the lcd, dram, or rom. wr# output active when the v r 4111 is writing data to the lcd, dram, or rom. lcdrdy input this is the lcd ready signal. set this signal as active when the lcd controller is ready to be accessed from the v r 4111. romcs (2:3)# output this function differs depending on how the dbus32 pin is set. when dbus32 = 1 it is the chip select signal for expansion rom/dram. when dbus32 = 0 it is a rom chip select signal. romcs (0:1)# output this is the rom chip select signal. uucas#/ mras3# output this function differs depending on how the dbus32 pin is set. when dbus32 = 1 this signal is active when a valid column address is output via the add bus during access of data (24:31) in the 32-bit data bus. this signal also becomes active if the bus that accesses the lcd is 32 bits wide, and if a valid address is output to the add bus when data (24:31) is accessed. when dbus32 = 0 this is the dram's ras signal. this signal is active when a valid row address is output via the add bus for the dram connected to the highest address. ulcas#/ mras2# output this function differs depending on how the dbus32 pin is set. when dbus32 = 1 this signal is active when a valid column address is output via the add bus during access of data (16:23) in the 32-bit data bus. this signal also becomes active if the bus that accesses the lcd is 32 bits wide, and if a valid address is output to the add bus when data (16:23) is accessed. when dbus32 = 0 this is the dram's ras signal. this signal is active when a valid row address is output via the add bus for the dram connected to the next-highest address.
data sheet u13211ej2v0ds00 11 m m m m pd30111 (2/2) signal name i/o function mras (0:1)# output this is the dram's ras-only signal. ucas# output this is the dram's cas signal. this signal is active when a valid column address is output via the add bus during access of data (8:15) in the dram. this signal also becomes active if the bus that accesses the lcd is 32 bits wide, and if a valid address is output to the add bus when data (8:15) is accessed. lcas# output this is the dram's cas signal. this signal is active when a valid column address is output via the add bus during access of data (0:7) in the dram. this signal also becomes active if the bus that accesses the lcd is 32 bits wide, and if a valid address is output to the add bus when data (0:7) is accessed. busclk output this is the system bus clock. it is used to output the clock that is s upplied to the controller on the system bus. the frequency to be output is determined according to the state of pins clksel2/txd, clksel1/rts#, and clksel0/dtr#. (see (5) rs-232c interface signals ) shb# output this is the system bus high-byte enable signal. during system bus access, this si gnal is active when the higher bytes are valid on the data bus. ior# output this is the system bus i/o r ead signal. it is active when the v r 4111 accesses the system bus to read data from an i/o port. iow# output this is the system bus i/o write si gnal. it is active when the v r 4111 accesses the system bus to write data to an i/o port. memr# output this is the system bus memory r ead signal. it is active when the v r 4111 accesses the system bus to r ead data from memory. memw# output this is the system bus memory write si gnal. it is active when the v r 4111 accesses the system bus to write data to memory. zws# input this is the system bus zero wait state si gnal. set this signal as active to enable the controller on the system bus to be accessed by the v r 4111 without a wait interval. rstout output this is the system bus reset si gnal. it is active when the v r 4111 resets the system bus controller. memcs16# input this is a dynamic bus sizing request signal. set this signal as active when system bus memory accesses data in 16-bit width m ode. iocs16# input this is a dynamic bus sizing request signal. set this signal as active when system bus i/o accesses data in 16-bit width m ode. iochrdy input this is the system bus r eady signal. set this signal as active when the system bus controller is ready to be accessed by the v r 4111. hldrq# input this is a hold request signal for the system bus and dram bus that is sent from an external bus master. hldack# output this is a hold acknowledge signal for the system bus and dram bus that is sent to an external bus master.
data sheet u13211ej2v0ds00 12 m m m m pd30111 (2) clock interface signals signal name i/o function rtcx1 input this is the 32.768-khz oscillator's input pin. it is connected to one side of a crystal resonator. rtcx2 output this is the 32.768-khz oscillator's output pin. it is connected to one side of a crystal resonator. clkx1 input this is the 18.432-mhz oscillator's input pin. it is connected to one side of a crystal resonator. clkx2 output this is the 18.432-mhz oscillator's output pin. it is connected to one side of a crystal resonator. firclk input this is the 48-mhz clock input pin. fix this at high level when fir is not used. (3) battery monitor interface signals signal name i/o function battinh/ battint# input this function differs depending on the state of the mpower pin. when mpower = 0 battinh function enables or disables starting of power application. 1: enables starting 0: disables starting when mpower = 1 battint# function this is an interrupt signal that is output when remaining battery power is low during normal operations. the external agent che cks the remaining battery power and asserts the signal at this pin if voltage sufficient for operations cannot be supplied. (4) initialization interface signals signal name i/o function mpower output indicates that the v r 4111 is operating. poweron output signal indicating that v r 4111 is to start activation. it is asserted active when start cause is detected, and deasserted inactive after battinh/battint# signal check has been completed. power input start signal of the v r 4111. rstsw# input reset signal of the v r 4111. rtcrst# input signal resetting rtc. when power is supplied to system for the first time, the external circuit should assert this pin active for about 600 ms.
data sheet u13211ej2v0ds00 13 m m m m pd30111 (5) rs-232c interface signals signal name i/o function rxd input this is a receive data signal. it is used when the rs-232c controller sends serial data to the v r 4111. cts# input this is the transmit enable (clear-to-send) signal. this signal is asserted when the rs- 232c controller is ready to receive transmission of serial data. dcd#/ gpio15 input this is a carrier detection signal. assert this signal active when valid serial data is being received. it is also used when detecting a power-on factor for the v r 4111. when this is not used as the dcd# signal, this can be used as an interrupt detection i/o signal for the giu unit. dsr# input this is the data set ready signal. assert this signal active to set up transmission and reception of serial data between the rs-232c controller and the v r 4111. this function differs depending on the operating status. during normal operation (output) these signals are used to perform serial communication. txd: this is a transmit data signal. it is used when the v r 4111 sends serial data to the rc-232c controller. rts#: this is a transmit request signal. this signal is asserted when the v r 4111 is ready to receive serial data from the rs-232c controller. dtr#: this is a terminal equipment ready signal. this signal is asserted when the v r 4111 is ready to transmit or receive serial data. at rtc reset (input) these signals (clksel (0:2)) are used to set the operating frequency of the cpu core and the busclk output frequency. these signals are sampled when the rtcrst# signal goes high. clksel (2:0) cpu core operating frequency (mhz) busclk output frequency (mhz) 1xx note rfu rfu 011 69.3 5.77 010 65.4 5.45 001 62.0 5.17 000 49.1 6.13 txd/clksel2, rts#/clksel1, dtr#/clksel0 i/o note do not set clksel2 to 1. remark x: dont care
data sheet u13211ej2v0ds00 14 m m m m pd30111 (6) irda interface signals signal name i/o function irdin input this is the irda serial data input signal. it is used when the irda controller sends the serial data to the v r 4111. both fir and sir can be used. however, if the irda controller used is made by hp, this signal should be used only for sir. firdin#/sel i/o this function differs according to the irda controller used. for details, see 15 siu (serial interface unit) . when an hp's controller is used firdin#: fir receive data input signal when a temic's controller is used sel: fir/sir switch signal output signal when a sharp's controller is used usage is prohibited. irdout# output this is the irda serial data output signal. it is used when the v r 4111 sends serial data to the irda controller. (7) debug serial interface signals signal name i/o function ddout/gpio44 output this is the debug serial data output signal. it is used when the v r 4111 sends serial data to an external debug serial controller. when this pin is not used as the ddout signal, it can be used as a general-purpose output port. ddin/gpio45 i/o this is the debug serial data input signal. it is used when an external debug serial controller sends serial data to the v r 4111. when this pin is not used as the ddin signal, it can be used as a general-purpose output port. drts#/gpio46 output this is a transmission request signal. the v r 4111 asserts this signal before sending serial data. when this pin is not used as the drts# signal, it can be used as a general-purpose output port. dcts#/gpio47 i/o this is a transmit acknowledge signal. the v r 4111 asserts this signal when it is ready to receive transmitted serial data. when this pin is not used as the dcts# signal, it can be used as a general-purpose output port. (8) keyboard interface signals signal name i/o function kport (0:7) input this is a keyboard scan data input signal. it is used to scan for pressed keys on the keyboard. kscan (0:11)/ gpio (32:43) output these signals are used as keyboard scan data output signals and a general-purpose output port. the scan line is set as active when scanning for pressed keys on the keyboard. pins that are not used for the key scan operation can be used as a general-purpose output port.
data sheet u13211ej2v0ds00 15 m m m m pd30111 (9) audio interface signals signal name i/o function audioin input this is an audio input signal. audioout output this is an audio output signal. analog signals that have been converted via the on-chip 10-bit d/a converter are output. (10) touch panel/general-purpose a/d interface signals signal name i/o function tpx (0:1) i/o these are i/o signals that are used for the touch panel. they use the voltage applied to the x coordinate and the voltage input to the y coordinate to detect which coordinates on the touch panel are being pressed. tpy (0:1) i/o these are i/o signals that are used for the touch panel. they use the voltage applied to the y coordinate and the voltage input to the x coordinate to detect which coordinates on the touch panel are being pressed. adin (0:2) input this is a general-purpose a/d input signal. (11) general-purpose i/o signals signal name i/o function gpio (0:3) i/o these are maskable activation factor input signals. after start-up, they are used as ordinary gpio pins. gpio (4:8) i/o these are general-purpose i/o pins. gpio (9:12) i/o these are maskable activation factor input signals. after start-up, they are used as ordinary gpio pins. gpio (13:14) i/o these are general-purpose i/o pins. gpio (16:31)/ data (16:31) i/o see (1) system bus interface signals in this section. gpio (32:43)/ kscan (0:11) output see (8) keyboard interface signals in this section. gpio44/ddout output see (7) debug serial interface signals in this section. gpio45/ddin i/o see (7) debug serial interface signals in this section. gpio46/drts# output see (7) debug serial interface signals in this section. gpio47/dcts# i/o see (7) debug serial interface signals in this section. gpio48/dbus32 i/o see (14) initialization signals in this section. gpio49 output this function differs depending on the operating status. during normal operation it can be used as a general-purpose output port. at rtc reset this pin functions as an input pin. input a low level to this pin. this signal is sampled when the rtcrst# signal goes high.
data sheet u13211ej2v0ds00 16 m m m m pd30111 (12) hsp modem interface signals signal name i/o function iring input this signal is asserted active when detecting the ring signal. ilcsense input handset detect signal offhook output on-hook relay control signal mute output modem speaker mute control signal aferst# output codec reset signal sdi input serial input signal from codec fs input frame synchronization signal from codec sdo output serial output signal to codec hspsclk input operation clock input of modem interface block for codec telcon output handset relay control signal hc0 output codec control signal hspmclk output clock output to codec opd# output this signal is asserted active when the power supply of codec or daa is on. (13) led interface signal signal name i/o function ledout# output this is an output signal for lighting leds. (14) initialization signals signal name i/o function dbus32/ gpio48 i/o this function differs depending on the operating status. during normal operation (output) this can be used as a general-purpose output port. at rtc reset (input) this can be used as the data-bus width switch signal. this signal is sampled when the rtcrst# signal goes high. 1: data bus is used in 32-bit width mode 0: data bus is used in 16-bit width mode mips16en input this signal enables or disables use of the mips16 instruction. this signal is sampled when the rtcrst# signal goes high. 1: enable use of the mips16 instruction 0: disables use of the mips16 instruction
data sheet u13211ej2v0ds00 17 m m m m pd30111 (15) dedicated v dd and gnd signals signal name power supply function v dd p 2.5 v v dd dedicated for the pll analog block. gndp 2.5 v gnd dedicated for the pll analog block. v dd pd 2.5 v v dd dedicated for the pll digital block. the function is the same as v dd 2. gndpd 2.5 v gnd dedicated for the pll digital block. the function is the same as gnd2. cv dd 3.3 v v dd dedicated for the oscillator. cgnd 3.3 v gnd dedicated for the oscillator. dv dd 3.3 v v dd dedicated for the d/a converter. the voltage applied to this pin becomes the maximum value for audioout's analog output. dgnd 3.3 v gnd dedicated for the d/a converter. the voltage applied to this pin becomes the minimum value for audioout's analog output. av dd 3.3 v v dd dedicated for the a/d converter. the voltage applied to this pin becomes the maximum voltage value for the ad interface signal. agnd 3.3 v gnd dedicated for the a/d converter. the voltage applied to this pin becomes the minimum voltage value detectable by the ad interface signals. piuv dd 3.3 v v dd dedicated for the touch panel interface. piugnd 3.3 v gnd dedicated for the touch panel interface. v dd 2 2.5 v normally, v dd of 2.5 v. gnd2 2.5 v normally, gnd of 2.5 v. v dd 3 3.3 v normally, v dd of 3.3 v. gnd3 3.3 v normally, gnd of 3.3 v. caution the v r 4111 has two types of power supplies. there are no restrictions as to the sequence in which these power supplies are applied. however, do not apply one type of power for more than one second while the other power supply is not applied.
data sheet u13211ej2v0ds00 18 m m m m pd30111 1.2 pin status in specific status (1/3) signal name after reset by rtcrst after reset by deadman's sw or rstsw in suspend mode in hibernate mode or on shutdown by hal timer during bus hold add (0:25) 0 0 note 1 0hi-z data (0:15) 0 0 note 1 0hi-z data (16:31)/ gpio (16:31) 0/ hi-z 0/ hi-z note 1 0/ hi-z hi-z/ note 1 lcdcs# hi-z 1 1 hi-z 1 rd# hi-z 1 1 hi-z hi-z wr# hi-z 1 1 hi-z hi-z lcdrdy CCCCC romcs (2:3)# hi-z note 2 note 2 note 2 note 2 romcs (0:1)# hi-z 1 1 hi-z 1 uucas#/mras3# note 3 note 4 00hi-z ulcas#/mras2# note 3 note 4 00hi-z mras (0:1)# 1 note 4 00hi-z ucas# 0 note 4 00hi-z lcas# 0 note 4 00hi-z busclk 0 0 note 1 0 note 5 shb# hi-z 1 1 hi-z hi-z ior# hi-z 1 1 hi-z hi-z iow# hi-z 1 1 hi-z hi-z memr# hi-z 1 1 hi-z hi-z memw# hi-z 1 1 hi-z hi-z zws# CCCCC rstout hi-z 1 0 hi-z note 6 notes 1. the previous fullspeed mode state is retained. 2. when these pins are used as chip select signals of rom/expansion rom, their function is the same as that of romcs (0:1)#. when they are used as ras signals of the expansion dram, their function is the same as that of mras (0:1)#. 3. when dbus32 = 1: outputs low level. when dbus32 = 0: outputs high level. 4. reset by rstsw# signal: this pin outputs low level (self-refresh function). reset by deadman's switch: this pin outputs high level. 5. bus hold from suspend mode: the previous fullspeed mode state is retained. bus hold from full speed mode or standby mode: outputs clocks. 6. normal operation is performed. remark 0: low-level output, 1: high-level output, hi-z: high impedance
data sheet u13211ej2v0ds00 19 m m m m pd30111 (2/3) signal name after reset by rtcrst after reset by deadman's sw or rstsw in suspend mode in hibernate mode or on shutdown by hal timer during bus hold iocs16# CCCCC memcs16# CCCCC iochrdy CCCCC hldrq# CCCCC hldack# hi-z 1 note 1 hi-z note 1 rtcx1 CCCCC rtcx2 CCCCC clkx1 CCCCC clkx2 CCCCC firclk CCCCC battinh/ battint#CCCCC mpower 01101 poweron 00000 power CCCCC rstsw# CCCCC rtcrst# CCCCC rxd CCCCC txd/clksel2 hi-z 1 1 1 note 1 rts#/clksel1 hi-z 1 1 1 note 1 cts# CCCCC dcd#/gpio15 CCCCC dtr#/clksel0 hi-z 1 1 1 note 1 dsr# CCCCC irdin CCCCC irdout# 0000 note 1 firdin#/sel hi-z hi-z note 2 hi-z note 2 ddin/ gpio45 note 3 C/ hi-z C/ note 2 C/ note 2 C/ note 2 C/ note 2 ddout/ gpio44 note 3 1/ 1 1/ note 2 1/ note 2 1/ note 2 1/ note 2 drts#/ gpio46 note 3 1/ 1 1/ note 2 1/ note 2 1/ note 2 1/ note 2 dcts#/ gpio47 note 3 C/ hi-z C/ note 2 C/ note 2 C/ note 2 C/ note 2 notes 1. normal operation is performed. 2. the previous fullspeed mode state is retained 3. whether these pins are used as function pins or output port pins can be selected by software. remark 0: low-level output, 1: high-level output, hi-z: high impedance
data sheet u13211ej2v0ds00 20 m m m m pd30111 (3/3) signal name after reset by rtcrst after reset by deadman's sw or rstsw in suspend mode in hibernate mode or on shutdown by hal timer during bus hold kport (0:7) CCCCC kscan (0:11)/ gpio (32:43) note 1 hi-z/ hi-z hi-z/ note 2 note 2 / note 2 hi-z/ note 2 note 3 audioout 0 0 note 2 0 note 3 tpx (0:1) 1 1 note 2 1 note 3 tpy (0:1) hi-z hi-z note 2 hi-z note 3 adin (0:2) CCCCC audioin CCCCC gpio (0:14) hi-z hi-z note 2 hi-z note 3 iring CCCCC ilcsense CCCCC offhook note 4 hi-z hi-z note 2 hi-z note 2 mute note 4 hi-z hi-z note 2 hi-z note 2 aferst# note 4 00 note 2 0 note 2 sdi CCCCC fs CCCCC sdo 0 0 note 2 0 note 2 hspsclk CCCCC telcon note 4 hi-z hi-z note 2 hi-z note 2 hc0 note 4 00 note 2 0 note 2 hspmclk note 4 00 note 2 0 note 2 opd# 0 0 note 2 0 note 2 ledout# 1 note 3 note 3 note 3 note 3 dbus32/ gpio48 note 5 hi-z/ hi-z hi-z/ note 2 note 2 / note 2 hi-z/ note 2 note 2 / note 2 mips16en hi-z hi-z hi-z hi-z hi-z gpio49 note 5 note 6 note 2 note 2 note 2 note 2 notes 1. whether these pins are used as function pins or output port pins can be selected by software. 2. the previous fullspeed mode state is retained. 3. normal operation is performed. 4. be sure to set the bsc bit of the hspint register (0x0c00 0020) to 1 at initialization. 5. this pin functions as an output port after rtc reset has been cleared. 6. this pin functions as an input pin. input a low level to this pin. remark 0: low-level output, 1: high-level output, hi-z: high impedance
data sheet u13211ej2v0ds00 21 m m m m pd30111 1.3 types of pin i/o circuits and recommended connection of unused pins (1/3) signal name internal process external process drive capacity i/o circuit type add (0:25) slew rate buffer C 120 pf a data (0:15) C C 40 pf a data (16:31)/ gpio (16:31) C note 1 40 pf a lcdcs# slew rate buffer C 40 pf a rd# slew rate buffer note 2 120 pf a wr# slew rate buffer note 2 120 pf a lcdrdy C note 3 Ca romcs (2:3)# slew rate buffer note 4 40 pf a romcs (0:1)# slew rate buffer C 40 pf a uucas#/mras3# slew rate buffer note 2 120 pf a ulcas#/mras2# slew rate buffer note 2 120 pf a mras (0:1)# slew rate buffer note 2 40 pf a ucas# slew rate buffer note 2 120 pf a lcas# slew rate buffer note 2 120 pf a busclk slew rate buffer C 40 pf a shb# slew rate buffer note 2 40 pf a ior# slew rate buffer note 2 40 pf a iow# slew rate buffer note 2 40 pf a memr# slew rate buffer note 2 40 pf a memw# slew rate buffer note 2 40 pf a zws# note 5 note 3 Ca rstout slew rate buffer pull-up 40 pf a iocs16# note 5 note 3 Ca memcs16# note 5 note 3 Ca iochrdy note 5 note 3 Ca notes 1. the data (16:31) pins of the v r 4111 function as gpio (16:31) when the width of the data bus is set to 16 bits. when using these pins as gpio (16:31), pull them up/down so that an intermediate level is not input to them. 2. externally pull up these pins when the bus hold function is used. 3. do not input an intermediate level to these pins. 4. externally pull up these pins when they are used as the ras signals of the extension dram. 5. an intermediate level can be input to these pins while the mpower pin outputs a low level.
data sheet u13211ej2v0ds00 22 m m m m pd30111 (2/3) signal name internal process external process drive capacity i/o circuit type hldrq# note 1 note 2 Ca hldack# slew rate buffer C 40 pf a rtcx1 C oscillator C C rtcx2 C oscillator C C clkx1 C oscillator C C clkx2 C oscillator C C firclk C note 3 Ca battinh/ battint# schmitt-triggered input C C b mpower C C 40 pf a poweron C C 40pf a power schmitt-triggered input C C b rstsw# schmitt-triggered input C C b rtcrst# schmitt-triggered input C C b rxd C C C a txd/clksel2 C pull-up/pull-down 40 pf a rts#/clksel1 C pull-up/pull-down 40 pf a cts# C C C a dcd#/gpio15 schmitt-triggered input pull-up C b dtr#/clksel0 C pull-up/pull-down 40 pf a dsr# C C C a irdin C pull-up C a irdout# C C 40 pf a firdin#/sel C pull-up/pull-down 40 pf a ddin/gpio45 C C 40 pf a ddout/gpio44 C C 40 pf a drts#/gpio46 C C 40 pf a dcts#/gpio47 C C 40 pf a notes 1. an intermediate level can be input to these pins while the mpower pin outputs a low level. 2. when bus hold function is used: pull up this pin. when bus hold function is not used: connect this pin to v dd . 3. when fir unit is used: connect an oscillator to this pin. when fir unit is not used: fix this pin to v dd .
data sheet u13211ej2v0ds00 23 m m m m pd30111 (3/3) signal name internal process external process drive capacity i/o circuit type kport (0:7) schmitt-triggered input, pull-down CCb kscan (0:11)/ gpio (32:43) C C 40 pf a audioout C note 1 Cf tpx (0:1) C C 120 pf or higher c tpy1 C C 120 pf or higher d tpy0 C C 120 pf or higher c adin (0:2) C C C e audioin C C C e gpio (0:14) schmitt-triggered input, note 2 note 2 40 pf b iring schmitt-triggered input pull-down C b ilcsense C pull-down C a offhook C C 40 pf a mute C C 40 pf a aferst# C C 40 pf a sdi C pull-up/pull-down C a fs C pull-up/pull-down C a sdo C C 40 pf a hspsclk C C C a telcon C C 40 pf a hc0 C C 40 pf a hspmclk C C 40 pf a opd# C C 40 pf a ledout# C C 40 pf a dbus32/ gpio48 C pull-up/pull-down 40 pf a mips16en C pull-up/pull-down 40 pf a gpio49 C pull-down C a notes 1. the output level of the audioout pin fluctuates with the external impedance. connect an operational amplifier with input characteristics of high impedance to this pin. 2. connecting an internal pull-up/pull-down resistor to the gpio (0:14) pins can be selected by software. when the internal pull-up/pull-down resistor is not used, connect an external pull-up/pull-down resistor to these pins.
data sheet u13211ej2v0ds00 24 m m m m pd30111 1.4 pin i/o circuits p-ch n-ch in + - v ref data output disable input enable v dd p-ch n-ch in/out type a pullup enable data open drain output disable pulldown enable v dd p-ch n-ch in/out v dd p-ch n-ch + - data output disable v ref in/out v dd p-ch n-ch p-ch n-ch + - data output disable v ref in/out v dd p-ch n-ch p-ch n-ch input enable n-ch analog output voltage out type d type e type f type b type c
data sheet u13211ej2v0ds00 25 m m m m pd30111 2. internal blocks for the internal block configuration, see the figure on page 6. 2.1 v r 4110 cpu core (1) cpu the cpu processes integer instructions and consists of a 64-bit register file, a 64-bit integer data bus, and a sum-of-products operation unit. (2) coprocessor 0 (cp0) the cp0 has a memory management unit (mmu) and an exception processing function. the mmu translates addresses and checks whether an access is made between different types (user, supervisor, or kernel) of memory segments. translation of virtual addresses to physical addresses is performed by tlb (high-speed translation lookaside buffer). (3) instruction cache the instruction cache has a 16-kbyte capacity, consisting of direct mapping, virtual index, and physical tag type. (4) data cache the data cache has an 8-kbyte capacity, consisting of direct mapping, virtual index, physical tag, and write back type. (5) cpu bus interface the cpu bus interface controls data transfer between the v r 4110 cpu core and bcu, which is one of the peripheral units. as the bus interface for the v r 4110 cpu core, two 32-bit address/data multiplexed buses for input and output, clock signals, and interrupt control signals are used. 2.2 clock generator the following clock inputs are oscillated to generate and supply clocks to internal units. 32.768-khz clock for rtc. the 32.768-khz clock generated by the crystal resonator is oscillated by the internal oscillator, and supplied to the rtc unit. 18.432-mhz clock for serial interface, touch panel interface, and reference operating clock of the v r 4111. the 18.432-mhz clock generated by the crystal resonator is oscillated by the internal oscillator, multiplied by pll (phase-locked loop), to generate the pipeline clock (pclock). the internal bus clock (tclock) is generated from pclock. 2.3 bcu (bus control unit) the bcu internally transfers data with the v r 4110 cpu core via sysad bus (internal). it also controls the lcd controller, dram, rom (flash memory or mask rom), and pcmcia controller connected to the system bus, and transfers data with the above devices via add and data buses.
data sheet u13211ej2v0ds00 26 m m m m pd30111 2.4 rtc (real-time clock unit) the rtc has a precise counter that operates with a 32.768-khz clock supplied from the clock generator. it also has several counters and compare registers for various interrupts. 2.5 dsu (deadman's switch unit) the dsu is used to check whether the processor is operating normally. if the software does not clear the register of this unit at specific intervals, the system is shut down. 2.6 icu (interrupt control unit) the icu controls interrupt requests generated from the external and internal sources of the v r 4111, and reports an interrupt request, if any, to the v r 4110 cpu core. 2.7 pmu (power management unit) the pmu outputs signals necessary for controlling the power of the entire system, including the v r 4111. it also controls the pll of the v r 4110 cpu core and the internal clocks (pclock, tclock, and masterout) in the power- saving mode. 2.8 dmaau (direct memory access address unit) the dmaau controls three types of dma transfer addresses. 2.9 dcu (direct memory access control unit) the dcu controls addresses of three types of dma transfers. 2.10 cmu (clock mask unit) the cmu controls supply of the clocks (tclock or masterout) from the v r 4110 cpu core to the internal peripheral units. 2.11 giu (general purpose i/o unit) giu controls forty-nine gpio pins. 2.12 aiu (audio interface unit) aiu performs microphone-input sampling and audio-signal output by controlling the internal a/d and d/a converters. 2.13 kiu (keyboard interface unit) the kiu has 8/10/12 scan lines and eight detection lines to detect input of 64/80/96 keys. it can also detect roll over of 2 or 3 keys by adding diodes.
data sheet u13211ej2v0ds00 27 m m m m pd30111 2.14 piu (touch panel interface unit) piu performs touch detection of the touch panel by controlling the internal a/d converter. 2.15 dsiu (debug serial interface unit) the dsiu is a serial interface for debugging and supports a transfer rate of up to 115 kbps. 2.16 siu (serial interface unit) the siu is a serial interface that is compatible with ns16550 and conforms to the rs-232c standards, and supports a transfer rate of up to 1.15 mbps. in addition, an irda serial interface that supports a transfer rate of 4 mbps using the fir unit is also included, though this irda serial interface is exclusively used with the rs-232c interface. 2.17 fir (fast irda interface unit) the fir unit is a unit to perform irda communication of 0.576 mbps to 4 mbps. this unit operates with a dedicated 48-mhz clock input. 2.18 hsp (host signal processing unit) the hsp unit is a unit for realizing a software modem. this unit controls interfacing between the cpu core and the codec devices. 2.19 led (led unit) the led unit is a unit for controlling the lighting of external leds.
data sheet u13211ej2v0ds00 28 m m m m pd30111 3. internal architecture 3.1 pipeline each instruction is executed in the following five steps: (1) if instruction fetch (2) rf register fetch (3) ex execution (4) dc data cache fetch (5) wb write back the v r 4111 has a five-stage pipeline. it takes five clocks to execute each instruction, but instructions can be executed in parallel. the pipeline clock, pclock, is determined by the setting of the clksel (0:2) pins. the following figure outlines the pipeline. figure 3-1. pipeline of v r 4111 (5-stage) pclock (internal) if rf ex dc wb if rf ex dc wb if rf ex dc wb if rf ex dc wb if rf ex dc wb current cpu cycle
data sheet u13211ej2v0ds00 29 m m m m pd30111 3.2 cpu registers figure 3-2 shows the cpu registers of the v r 4111. the bit width of these registers is determined by the operation mode of the processor (32 bits in 32-bit mode or 64 bits in 64-bit mode). of the 32 general-purpose registers, the following two have a special function. register r0: the contents of this register are always 0. to discard the result of an operation, describe this register as the target of an instruction. when the value 0 is necessary, this register can also be used as a source register. register r31: this is a link register used by link instructions, such as the jump and link (jal) instruction. r31 can be used by other instructions. however, be careful that use of the register by a link instruction will not coincide with use of the register for other operations. the two multiplication/division registers (hi and lo) store the result of a multiplication or sum-of-products operation, or the quotient (lo) and remainder (hi) resulting from division. because the v r 4111 does not support floating-point instructions, it is not provided with the 32 floating-point general-purpose registers (fgr) found in the v r 4300 tm and v r 4400 tm . the v r 4111 does not have a program status word (psw). the function of psw is substituted by the status registers and cause registers incorporated in the system control coprocessor (cp0). remark the load link bit (ll bit) used with synchronization instructions (ll and sc) for multiprocessor supported by the v r 4300 and v r 4400 is not provided in the v r 4111 (refer to 3.3.1 (2) deletion of multiprocessor instructions ). figure 3-2. cpu registers when the mips16 instruction set (refer to 3.3.2 ) is used, eight of the above general registers can be used. the special instruction of mips16 implicitly uses some general-purpose registers and the special registers. the register set for the mips16 instruction set is shown below. 63 32 31 32 31 0 63 0 r2 hi r1 r29 r30 r31= linkaddress lo pc 63 32 31 0 63 32 31 0 program counter multiplication/division registers r0 = 0 general-purpose registers
data sheet u13211ej2v0ds00 30 m m m m pd30111 table 3-1. register set when mips16 instruction set is used (a) general registers mips16 instruction register no. 32-bit instruction register no. symbol description 0 16 s0 general-purpose register 1 17 s1 general-purpose register 2 2 v0 general-purpose register 3 3 v1 general-purpose register 4 4 a0 general-purpose register 5 5 a1 general-purpose register 6 6 a2 general-purpose register 7 7 a3 general-purpose register C 24 t8 mips16 condition code register. bteqz, btnez, cmp, cmpi, slt, sltu, slti, and sltiu instructions are implicitly referenced. C 29 sp stack pointer register C 31 ra return address register (b) special registers symbol description pc program counter. the pc-relative add instruction and load instruction can access this register. hi the higher word of the multiply or divide result is inserted. lo the lower word of the multiply or divide result is inserted. remark the symbols are the general assembler symbols. 3.3 outline of instruction set basically, the instruction set of the v r 4111 conforms to the mips i, ii, and iii instruction sets. in addition, the mips16 instruction set whose instruction code length is fixed to 16 bits is supported. for details of each instruction set, refer to v r 4111 users manual . 3.3.1 mips iii instruction set the mips iii instruction set is different in the v r 4111 compared to in other processors in the v r series in the following four points. note that the difference between the v r 4100 tm and v r 4111 is that the v r 4111 can manage operations including peripheral functions by using power mode instructions (refer to (4) ). (1) deletion of floating-point (fpu) instructions because the v r 4111 does not have a floating-point unit, it does not support fpu instructions. if an fpu instruction is encountered, therefore, a reserved instruction exception occurs. if it is necessary to use an fpu instruction, emulate the instruction in software in an exception handler.
data sheet u13211ej2v0ds00 31 m m m m pd30111 (2) deletion of multiprocessor instructions the v r 4111 does not support a multiprocessor operating environment. if a synchronization support instruction (ll or sc instruction) defined by mips ii and iii isa is encountered, a reserved instruction exception occurs. in addition, the load link bit (ll bit) is also unavailable. the v r 4111 executes all load/store instructions in the programmed sequence. therefore, the sync instruction is treated as a nop instruction. (3) addition of sum-of-products instructions the v r 4111 has a dedicated sum-of-products operation core in the cpu and additional integer sum-of- products operation instructions, in order to execute sum-of-products operation at high speeds. note that these instructions are not correctly executed with any other processors in the v r series. the operations by the sum-of-products instructions are as follows: (a) madd16 (multiply and add 16-bit integer) this instruction multiplies the contents of general-purpose register rs by the contents of general-purpose register rt. both the operands are treated as signed 16-bit integers. bits 62 through 15 of both the operands must be sign-extended. the result of the multiplication is added to a 64-bit value combining special registers hi and lo. the lower word (64 bits) of the result is loaded to special register lo, and the higher word is loaded to hi. an integer overflow exception does not occur. figure 3-3 outlines the operation of the madd16 instruction. figure 3-3. operation of madd16 instruction rs rt 31 15 general-purpose register file mul add hi lo 63 31 higher lower (b) dmadd16 (doubleword multiply and add 16-bit register) this instruction multiplies the contents of general-purpose register rs by the contents of general-purpose register rt. both the operands are treated as signed 16-bit integers. bits 62 through 15 of both the operands must be sign-extended. the result of the multiplication is added to the value of special register lo. the result of the addition is treated as a signed integer. the 64-bit result is loaded to special register lo. an integer overflow exception does not occur. this operation is defined in the 64-bit mode and 32-bit kernel mode. if this instruction is encountered in the 32-bit user/supervisor mode, a reserved instruction exception occurs.
data sheet u13211ej2v0ds00 32 m m m m pd30111 (4) addition of power mode instructions the v r 4111 supports three power modes to lower the power consumption, and therefore, has dedicated instructions that set these modes. note that the power mode instructions are not correctly executed by any other processors in the v r series. the operations of the power mode instructions are as follows: (a) standby this instruction places the processor in the standby mode from the fullspeed mode. when instruction execution has proceeded to the wb stage, and the sysad bus (internal) has entered the idle status, the internal clock is fixed to high level, and the pipeline operation is stopped. in the standby mode, the pll, clocks related to timers/interrupts, and interface clocks to the peripheral function blocks (tclock and masterout) operate normally. when the processor is in the standby mode it is returned to the fullspeed mode by any interrupt including an internally generated timer interrupt. (b) suspend this instruction places the processor in the suspend mode from the fullspeed mode. when instruction execution has proceeded to the wb stage, and the sysad bus has entered the idle status, the internal clock and tclock are fixed to high level, and the pipeline operation and interfacing to the peripheral function blocks are stopped. in the suspend mode, the pll, clocks related to timers/interrupts, and masterout operate normally. the processor remains in the suspend mode until it accepts an interrupt. when the processor accepts an interrupt, it returns to the fullspeed mode. (c) hibernate this instruction places the processor in the hibernate mode from the fullspeed mode. when instruction execution has proceeded to the wb stage, and the sysad bus has entered the idle status, all the clocks are fixed to high level, and the pipeline operation is stopped. the processor remains in the hibernate mode until either the power pin is asserted active or the wakeup timer interrupt occurs. the processor returns to the fullspeed mode when the power pin is asserted active, when the wakeup timer interrupt occurs, or when the dcd# pin is asserted active. the cpu and peripheral units, including clock-related units, stop their operations in hibernate mode. 3.3.2 mips16 instruction set mips16 is an instruction set using 16-bit instructions. by using this instruction set, the memory capacity can be substantially reduced and the system cost can be lowered. mips16 is compatible with the mips i, ii, and iii instruction sets, and can be used with the existing instruction codes. moreover, the instruction length can be changed between 32 bits and 16 bits. caution the 16-bit instruction codes can be executed only by a processor that supports the mips16 instruction set. at present, the mips16 instruction set is supported only by products employing the v r 4110 core. therefore, the v r 4111 can execute a program using the existing 32-bit instructions without any modification, but the other processors (such as the v r 4100 and v r 4102 tm ) cannot execute a v r 4111 program including the 16-bit instructions.
data sheet u13211ej2v0ds00 33 m m m m pd30111 3.4 system control coprocessor (cp0) cp0 supports memory management, address translation, exception processing, and privilege operations. cp0 has the registers shown in table 3-2, and a 32-entry tlb. the basic configuration of the cp0 registers of the v r 4111 is the same as that of the v r 4300 and v r 4400. however, because the number of entries of tlb, page size, cache size, physical address space, and system interface differ between the v r 4111 and v r 4300/v r 4400, the bit configuration and settings differ. for details, refer to v r 4111 user's manual . 3.4.1 cp0 registers all the cp0 registers that can be used with the v r 4111 are shown below. writing to or reading from an unused register (rfu) is undefined. in the 32-bit mode, the higher 32 bits of 64-bit registers are masked. figure 3-4. cp0 registers and tlb entry lo0 2* entry hi 10* entry lo1 3* index 0* random 1* page mask 5* wired 6* prid 15* config 16* tag hi 29* tag lo 28* lladdr 17* tlb 31 00 127/255 ("safe" entry) context 4* badvaddr 8* count 9* compare 11* cause 13* status 12* epc 14* watch lo 18* x context 20* parity error 26* watch hi 19* cache error 27* error epc 30* registers used for memory management system registers used for exception processing remark "*" indicates the register number.
data sheet u13211ej2v0ds00 34 m m m m pd30111 table 3-2. cp0 registers no. register description 0 index programmable pointer to tlb array 1 random dummy random pointer to tlb array (read-only) 2 entry lo0 latter half of tlb entry for even-number vpn 3 entry lo1 latter half of tlb entry for odd-number vpn 4 context pointer to virtual pte table of kernel in 32-bit mode 5 page mask specifies page size 6 wired number of wired tlb entries 7 C rfu (reserved for future use) 8 badvaddr indicates virtual address at which error occurs last 9 count timer count 10 entry hi first half of tlb entry (including asid) 11 compare timer compare value 12 status sets operation status 13 cause indicates cause of last exception 14 epc exception program counter 15 prld processor revision id 16 config sets memory system mode 17 lladdr rfu 18 watch lo lower bits of memory reference trap address 19 watch hi higher bits of memory reference trap address 20 x context pointer to virtual pte table of kernel in 64-bit mode 21 to 25 C rfu 26 parity error note parity bit of cache 27 cache error note error and status register of cache 28 tag lo cache tag register, low 29 tag hi cache tag register, high (reserved register) 30 error epc error exception program counter 31 C rfu note these errors are defined to maintain compatibility between the v r 4100 and v r 4111, and are not used by the hardware of the v r 4111.
data sheet u13211ej2v0ds00 35 m m m m pd30111 3.5 data format and addressing the v r 4111 uses the following four data formats: double word (64 bits) word (32 bits) half word (16 bits) byte (8 bits) the byte ordering is set by the be bit of the config register. with the current v r 4111, set little endian. the byte ordering (endian) can be inverted during operation by setting the re bit of the status register. however, be sure not to set this to 1 with the current v r 4111. figure 3-5. byte address in word: little endian 31 24 23 16 15 0 higher address lower address 15 14 13 12 11 10 9 8 7654 3210 word address 12 8 4 0 8 7 remarks 1. the least significant byte is the lowest address. 2. a word is addressed by the address of the least significant byte. figure 3-6. byte address in double word: little endian higher address lower address double word address 16 8 0 63 32 31 0 word half word byte 23 22 15 7 14 6 21 13 5 20 12 4 19 11 3 18 10 2 17 9 1 16 8 0 16 15 8 7 remarks 1. the least significant byte is the lowest address. 2. a word is addressed by the address of the least significant byte.
data sheet u13211ej2v0ds00 36 m m m m pd30111 3.6 virtual storage the v r 4111 has a virtual storage management mechanism using tlb. virtual addresses are used for address management by software or address calculation of the pipeline. to access memories for program fetch and data access, and internal i/o and external i/o, physical addresses translated by tlb are used. note that part of the virtual address space is not translated by tlb, but is translated to physical addresses by merely changing specific addresses. if only this part of the address space is used, the v r 4111 can be treated in the same manner as a cpu that operates with physical addresses. 3.6.1 virtual address space the v r 4111 has two operation modes, 32-bit mode and 64-bit mode, and three types of operating modes: user mode, supervisor mode, and kernel mode. the virtual address space in each mode is shown below. figure 3-7. user mode address space note in the 32-bit mode, the value of bit 31 is sign-extended to bits 32 through 63. for details, refer to v r 4111 user's manual . 32 bits note address error 2 gbytes w/tlb mapping useg 64 bits address error 1 tbyte w/tlb mapping xuseg f ff f f f f f f f f f f f f f 0 x 0 00 0 0 0 0 0 0 0 0 1 0 0 0 0 0 x f 0f f f f f f f f f 0 0 0 0 0 0 x 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x ff f f f f f f 0 x 80 0 0 0 0 0 0 0 x 7f f f f f f f 0 x 00 0 0 0 0 0 0 0 x
data sheet u13211ej2v0ds00 37 m m m m pd30111 figure 3-8. supervisor mode address space note in the 32-bit mode, the value of bit 31 is sign-extended to bits 32 through 63. for details, refer to v r 4111 user's manual . 64 bits address error 0.5 gbytes w/tlb mapping address error 1 tbyte w/tlb mapping address error 1 tbyte w/tlb mapping xsseg csseg xsuseg 32 bits note address error address error 2 gbytes w/tlb mapping sseg suseg 0.5 gbytes w/tlb mapping f ff f f f f f f f f f f f f f 0 x ff f f f f f f 0 x 0 f0 0 0 0 0 0 e f f f f f f f 0 x e0 0 0 0 0 0 0 0 x f ff f f f f f d f f f f f f f 0 x df f f f f f f 0 x 0 f0 0 0 0 0 0 c f f f f f f f 0 x c0 0 0 0 0 0 0 0 x f ff f f f f f b f f f f f f f 0 x bf f f f f f f 0 x 0 40 0 0 0 0 0 0 0 0 1 0 0 0 0 0 x f 4f f f f f f f f f 0 0 0 0 0 0 x 0 40 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x 80 0 0 0 0 0 0 0 x f 3f f f f f f f f f f f f f f 0 x 7f f f f f f f 0 x 0 00 0 0 0 0 0 0 0 0 1 0 0 0 0 0 x f 0f f f f f f f f f 0 0 0 0 0 0 x 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x 00 0 0 0 0 0 0 0 x
data sheet u13211ej2v0ds00 38 m m m m pd30111 figure 3-9. kernel mode address space notes 1. in the 32-bit mode, the value of bit 31 is sign-extended to bits 32 through 63. for details, refer to v r 4111 user's manual . 2. whether this area is used as a cache area is specified by the k0 field of the config register. 64 bits 0.5 gbytes w/tlb mapping 0.5 gbytes w/tlb mapping 0.5 gbytes w/o tlb mapping uncacheable 0.5 gbytes w/o tlb mapping cacheable note 2 address error w/tlb mapping address error 1 tbyte w/tlb mapping address error 1 tbyte w/tlb mapping ckseg cksseg ckseg1 ckseg0 xkseg xkuseg xksseg 32 bits note 1 0.5 gbytes w/tlb mapping 0.5 gbytes w/o tlb mapping cacheable note 2 2 gbytes w/tlb mapping kseg3 ksseg kuseg 0.5 gbytes w/tlb mapping kseg1 kseg0 0.5 gbytes w/o tlb mapping uncacheable w/o tlb mapping (for details, refer to figure 3-10. ) xkphys f ff f f f f f f f f f f f f f 0 x ff f f f f f f 0 x 0 f0 0 0 0 0 0 f f f f f f f f 0 x f ff f f f f f d f f f f f f f 0 x 0 f0 0 0 0 0 0 c f f f f f f f 0 x e0 0 0 0 0 0 0 0 x f ff f f f f f b f f f f f f f 0 x df f f f f f f 0 x 0 f0 0 0 0 0 0 a f f f f f f f 0 x f ff f f f f f 9 f f f f f f f 0 x 0 f0 0 0 0 0 0 8 f f f f f f f 0 x c0 0 0 0 0 0 0 0 x f ff f f f f f 7 f f f f f f f 0 x bf f f f f f f 0 x 0 c0 0 0 0 0 0 8 f f 0 0 0 0 0 0 x f cf f f f f f 7 f f 0 0 0 0 0 0 x 0 c0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x a0 0 0 0 0 0 0 0 x f bf f f f f f f f f f f f f f 0 x 9f f f f f f f 0 x 0 80 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x f 7f f f f f f f f f f f f f f 0 x 0 40 0 0 0 0 0 0 0 0 1 0 0 0 0 0 x 80 0 0 0 0 0 0 0 x f 4f f f f f f f f f 0 0 0 0 0 0 x 7f f f f f f f 0 x 0 40 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x f 3f f f f f f f f f f f f f f 0 x 0 00 0 0 0 0 0 0 0 0 1 0 0 0 0 0 x f 0f f f f f f f f f 0 0 0 0 0 0 x 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x 00 0 0 0 0 0 0 0 x
data sheet u13211ej2v0ds00 39 m m m m pd30111 figure 3-10. details of xkphys area address error 4 gbytes w/o tlb mapping cacheable address error 4 gbytes w/o tlb mapping cacheable address error 4 gbytes w/o tlb mapping cacheable address error address error address error 4 gbytes w/o tlb mapping uncacheable address error 4 gbytes w/o tlb mapping uncacheable address error 4 gbytes w/o tlb mapping uncacheable f bf f f f f f f f f f f f f f 0 x 0 b0 0 0 0 0 0 0 1 0 0 0 0 0 8 0 x f bf f f f f f f 0 0 0 0 0 0 8 0 x 0 b0 0 0 0 0 0 0 0 0 0 0 0 0 8 0 x f bf f f f f f f f f f f f f 7 0 x 0 b0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 x f bf f f f f f f 0 0 0 0 0 0 0 0 x 0 b0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x f af f f f f f f f f f f f f f 0 x 0 a0 0 0 0 0 0 0 1 0 0 0 0 0 8 0 x f af f f f f f f 0 0 0 0 0 0 8 0 x 0 a0 0 0 0 0 0 0 0 0 0 0 0 0 8 0 x f af f f f f f f f f f f f f 7 0 x 0 a0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 x f af f f f f f f 0 0 0 0 0 0 0 0 x 0 a0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x f 9f f f f f f f f f f f f f f 0 x 0 90 0 0 0 0 0 0 1 0 0 0 0 0 8 0 x f 9f f f f f f f 0 0 0 0 0 0 8 0 x 0 90 0 0 0 0 0 0 0 0 0 0 0 0 8 0 x f 9f f f f f f f f f f f f f 7 0 x 0 90 0 0 0 0 0 0 1 0 0 0 0 0 0 0 x f 9f f f f f f f 0 0 0 0 0 0 0 0 x 0 90 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x f 8f f f f f f f f f f f f f f 0 x 0 80 0 0 0 0 0 0 1 0 0 0 0 0 8 0 x f 8f f f f f f f 0 0 0 0 0 0 8 0 x 0 80 0 0 0 0 0 0 0 0 0 0 0 0 8 0 x f 8f f f f f f f f f f f f f 7 0 x 0 80 0 0 0 0 0 0 1 0 0 0 0 0 0 0 x f 8f f f f f f f 0 0 0 0 0 0 0 0 x 0 80 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x 4 gbytes w/o tlb mapping cacheable 4 gbytes w/o tlb mapping cacheable 3.6.2 address translation virtual addresses are translated into physical addresses by the internal tlb (translation lookaside buffer) in page units. the tlb has a full-associative configuration and has 64 entries at the virtual address side and 32 entries at the physical address side. the page size is variable from 1 kbyte to 256 kbytes. if a tlb entry is not found, a tlb refill exception occurs in the 32-bit mode, and an xtlb refill exception occurs in the 64-bit mode. change the contents of the tlb in software. the following figure outlines address translation.
data sheet u13211ej2v0ds00 40 m m m m pd30111 figure 3-11. outline of address translation y+8 y+1 y x+1 x 0 xC1 31 0 asid vpn offset virtual address <1> <2> <3> selector <4> 31 x xC1 0 tlb x = 10, 12, 14, 16, 18 y = 31 (in 32-bit mode) 63 (in 64-bit mode) physical address <1> a virtual address page number (vpn) is compared with a vpn in tlb. <2> if the two vpns match, a page frame number (pfn) indicating the higher bits of a physical address is output to the selector. <3> if the lowest 1 bit of vpn is 0, an even page is selected; if it is 1, an odd page is selected. the selected page is output to the higher bits of the physical address. <4> the offset is output to the lower bits of the physical address without going through tlb. the tlb entry is read or written by loading/storing between the tlb entry indicated by the index register and the random register, entry hi, entry lo1, entry lo0, and page mask registers. how the tlb is manipulated is illustrated below. figure 3-12. outline of tlb manipulation entry lo0 register page mask register entry lo1 register entry hi register index register random register
data sheet u13211ej2v0ds00 41 m m m m pd30111 3.7 physical address space using a 32-bit address, the processor physical address space encompasses 4 gbytes. the v r 4111 uses this 4- gbyte address space as shown in figure 3-13. figure 3-13. v r 4111 physical address space mirror image of 0x0000 0000 to 0x1fff ffff area 3.5 gbytes rom area (including boot rom) 128 mbytes system bus i/o area (isa i/o) 64 mbytes system bus memory area (isa memory) 64 mbytes rfu 48 mbytes internal i/o area 1 16 mbytes internal i/o area 2 16 mbytes lcd/high-speed system bus memory area 16 mbytes rfu 96 mbytes dram area 64 mbytes 0xffff ffff 0x2000 0000 0x1fff ffff 0x1800 0000 0x17ff ffff 0x1400 0000 0x13ff ffff 0x1000 0000 0x0fff ffff 0x0d00 0000 0x0cff ffff 0x0c00 0000 0x0bff ffff 0x0b00 0000 0x0aff ffff 0x0a00 0000 0x09ff ffff 0x0400 0000 0x03ff ffff 0x0000 0000
data sheet u13211ej2v0ds00 42 m m m m pd30111 3.7.1 rom address space the rom address space differs depending on the bit width of the memory data bus and the capacity of the rom being used. the bit width of the memory data bus is specified by the setting of the dbus32 pin. the rom capacity is set via the rom64 bit of the bcucntreg1 register or the ext_rom64 bit of the bcucntreg3 register. the physical addresses of the rom space are listed below. table 3-3. rom addresses (when using 16-bit data bus) physical address add (25:0) when using 32-mbit rom (dbus32 = 0, rom64 = 0) when using 64-mbit rom (dbus32 = 0, rom64 = 1) 0x1fff ffff to 0x1fc0 0000 0x3ff ffff to 0x3c0 0000 bank 3 (romcs3#) 0x1fbf ffff to 0x1f80 0000 0x3bf ffff to 0x380 0000 bank 2 (romcs2#) bank 3 (romcs3#) 0x1f7f ffff to 0x1f40 0000 0x37f ffff to 0x340 0000 bank 1 (romcs1#) 0x1f3f ffff to 0x1f00 0000 0x33f ffff to 0x300 0000 bank 0 (romcs0#) bank 2 (romcs2#) 0x1eff ffff to 0x1e80 0000 0x2ff ffff to 0x280 0000 bank 1 (romcs1#) 0x1e7f ffff to 0x1e00 0000 0x27f ffff to 0x200 0000 bank 0 (romcs0#) 0x1dff ffff to 0x1800 0000 0x1ff ffff to 0x000 0000 rfu rfu
data sheet u13211ej2v0ds00 43 m m m m pd30111 table 3-4. rom addresses (when using 32-bit data bus) (a) when using 32-mbit expansion rom physical address add (25:0) when using 32-mbit rom (dbus32 = 1, rom64 = 0, ext_rom64 = 0 ) when using 64-mbit rom (dbus32 = 1, rom64 = 1, ext_rom64 = 0 ) 0x1fff ffff to 0x1f80 0000 0x3ff ffff to 0x380 0000 bank 1 (romcs1#) 0x1f7f ffff to 0x1f00 0000 0x37f ffff to 0x300 0000 bank 0 (romcs0#) bank 1 (romcs1#) 0x1eff ffff to 0x1e80 0000 0x2ff ffff to 0x280 0000 bank 3 (romcs3#) note 0x1e7f ffff to 0x1e00 0000 0x27f ffff to 0x200 0000 bank 2 (romcs2#) note bank 0 (romcs0#) 0x1dff ffff to 0x1d80 0000 0x1ff ffff to 0x180 0000 bank 3 (romcs3#) note 0x1d7f ffff to 0x1d00 0000 0x17f ffff to 0x100 0000 bank 2 (romcs2#) note 0x1cff ffff to 0x1800 0000 0x0ff ffff to 0x000 0000 rfu rfu (b) when using 64-mbit expansion rom physical address add (25:0) when using 32-mbit rom (dbus32 = 1, rom64 = 0, ext_rom64 = 1 ) when using 64-mbit rom (dbus32 = 1, rom64 = 1, ext_rom64 = 1 ) 0x1fff ffff to 0x1f80 0000 0x3ff ffff to 0x380 0000 bank 1 (romcs1#) 0x1f7f ffff to 0x1f00 0000 0x37f ffff to 0x300 0000 bank 0 (romcs0#) bank 1 (romcs1#) 0x1eff ffff to 0x1e00 0000 0x2ff ffff to 0x200 0000 bank 3 (romcs3#) note bank 0 (romcs0#) 0x1dff ffff to 0x1d00 0000 0x1ff ffff to 0x100 0000 bank 2 (romcs2#) note bank 3 (romcs3#) note 0x1cff ffff to 0x1c00 0000 0x0ff ffff to 0x000 0000 bank 2 (romcs2#) note 0x1bff ffff to 0x1800 0000 C rfu rfu note can be used exclusively from the expansion dram.
data sheet u13211ej2v0ds00 44 m m m m pd30111 3.7.2 internal i/o space the v r 4111 has two types of internal i/o spaces. each of these spaces in the internal i/o space are described below. table 3-5. internal i/o space 1 physical address internal i/o 0x0bff ffff to 0x0c00 0080 rfu 0x0c00 007f to 0x0c00 0060 fir2 0x0c0 0005f to 0x0c00 0040 fir 0x0c00 003f to 0x0c00 0020 hsp (software modem interface) 0x0c00 001f to 0x0c00 0000 siu (16550) table 3-6. internal i/o space 2 physical address internal i/o 0x0bff ffff to 0x0b00 0300 rfu 0x0b00 02ff to 0x0b00 02e0 giu2 0x0b00 02df to 0x0b00 02c0 pmu2 0x0b00 02bf to 0x0b00 02a0 piu2 0x0b00 029f to 0x0b00 0280 rfu 0x0b00 027f to 0x0b00 0260 a/d test 0x0b00 025f to 0x0b00 0240 led 0x0b00 023f to 0x0b00 0220 rfu 0x0b00 021f to 0x0b00 0200 icu2 0x0b00 01ff to 0x0b00 01e0 rfu 0x0b00 01df to 0x0b00 01c0 rtc2 0x0b00 01bf to 0x0b00 01a0 dsiu 0x0b00 019f to 0x0b00 0180 kiu 0x0b00 017f to 0x0b00 0160 aiu 0x0b00 015f to 0x0b00 0140 rfu 0x0b00 013f to 0x0b00 0120 piu1 0x0b00 011f to 0x0b00 0100 giu1 0x0b00 00ff to 0x0b00 00e0 dsu 0x0b00 00df to 0x0b00 00c0 rtc1 0x0b00 00bf to 0x0b00 00a0 pmu 0x0b00 009f to 0x0b00 0080 icu1 0x0b00 007f to 0x0b00 0060 cmu 0x0b00 005f to 0x0b00 0040 dcu 0x0b00 003f to 0x0b00 0020 dmaau 0x0b00 001f to 0x0b00 0000 bcu
data sheet u13211ej2v0ds00 45 m m m m pd30111 3.7.3 dram address space the dram address space differs depending on the bit width of the memory data bus and the capacity of the dram being used. the bit width of the memory data bus is specified by the setting of the dbus32 pin. the dram capacity is set via the dram64 bit of bcucntreg1 register or ext_dram64 bit of bcucntreg3 register. the physical addresses of the dram space are listed in tables 3-7 and 3-8. table 3-7. dram addresses (when using 16-bit data bus) physical address when using 16-mbit dram (dbus32 = 0, dram64 = 0) when using 64-mbit dram (dbus32 = 0, dram64 = 1) 0x03ff ffff to 0x0200 0000 rfu 0x01ff ffff to 0x0180 0000 bank 3 (mras3#/uucas#) 0x017f ffff to 0x0100 0000 bank 2 (mras2#/ulcas#) 0x00ff ffff to 0x0080 0000 rfu bank 1 (mras1#) 0x007f ffff to 0x0060 0000 bank 3 (mras3#/uucas#) 0x005f ffff to 0x0040 0000 bank 2 (mras2#/ulcas#) 0x003f ffff to 0x0020 0000 bank 1 (mras1#) 0x001f ffff to 0x0000 0000 bank 0 (mras0#) bank 0 (mras0#)
data sheet u13211ej2v0ds00 46 m m m m pd30111 table 3-8. dram addresses (when using 32-bit data bus) (a) when using 16-mbit expansion dram physical address when using 16-mbit dram (dbus32 = 1, dram64 = 0, ext_dram64 = 0) when using 64-mbit dram (dbus32 = 1, dram64 = 1, ext_dram64 = 0) 0x03ff ffff to 0x0280 0000 rfu 0x027f ffff to 0x0240 0000 bank 3 (romcs3#) note 0x023f ffff to 0x0200 0000 bank 2 (romcs2#) note 0x01ff ffff to 0x0180 0000 0x017f ffff to 0x0100 0000 rfu bank 1 (mras1#) 0x00ff ffff to 0x00e0 0000 0x00df ffff to 0100c0 0000 bank 3 (romcs3#) note 0x00bf ffff to 0x00a0 0000 0x009f ffff to 0x0080 0000 bank 2 (romcs2#) note 0x007f ffff to 0x0060 0000 0x005f ffff to 0x0040 0000 bank 1 (mras1#) 0x003f ffff to 0x0020 0000 0x001f ffff to 0x0000 0000 bank 0 (mras0#) bank 0 (mras0#) (b) when using 64-mbit expansion dram physical address when using 16-mbit dram (dbus32 = 1, dram64 = 0, ext_dram64 = 1) when using 64-mbit dram (dbus32 = 1, dram64 = 1, ext_dram64 = 1) 0x03ff ffff to 0x0300 0000 bank 3 (romcs3#) note 0x02ff ffff to 0x0280 0000 rfu 0x027f ffff to 0x0200 0000 bank 2 (romcs2#) note 0x01ff ffff to 0x0180 0000 bank 3 (romcs3#) note 0x017f ffff to 0x0100 0000 bank 1 (mras1#) 0x00ff ffff to 0x0080 0000 bank 2 (romcs2#) note 0x007f ffff to 0x0060 0000 0x005f ffff to 0x0040 0000 bank 1 (mras1#) 0x003f ffff to 0x0020 0000 0x001f ffff to 0x0000 0000 bank 0 (mras0#) bank 0 (mras0#) note can be used exclusively from the expansion rom.
data sheet u13211ej2v0ds00 47 m m m m pd30111 3.8 cache (1) instruction cache the instruction cache has the following features: on-chip cache memory capacity: 16 kbytes direct mapping mode virtual index address physical tag check 4-word (16-byte) cache line figure 3-14. format of instruction cache ptag: physical tag (bits 31 to 10 of physical address) v: valid bit data: cache data 1,023 150 149 0 0 122 ptag data 128 v 128 127
data sheet u13211ej2v0ds00 48 m m m m pd30111 (2) data cache the data cache has the following features: on-chip cache memory capacity: 8 kbytes write back direct mapping mode virtual index address physical tag check 4-word (16-byte) cache line figure 3-15. format of data cache w: write back bit v: valid bit d: dirty bit ptag: physical tag (bits 31 to 10 of physical address) data: cache data 3.9 exception processing the v r 4111 enters the kernel mode in which interrupts are disabled when an exception occurs, and executes an exception handler from a fixed exception vector address. to restore from the exception, the program counter, operating mode, and interrupt enable information must be restored to the original status. save this information when the interrupt occurs. when an interrupt occurs, the epc register holds the address of the instruction that has caused the exception, or the address of the instruction immediately before if the exception has occurred in the branch delay slot. this means that the epc register stores the address from which execution is to be started after the exception has been processed. after reset and on occurrence of nmi, the epc register holds a restart address. 511 152 0 0 1 ptag data 128 w 151 1 v 150 1 d 128 127 22 149
data sheet u13211ej2v0ds00 49 m m m m pd30111 table 3-9. types of exceptions exception symbol description cold reset C this exception occurs if the coldreset# (internal) and reset# (internal) signals are simultaneously asserted active (for details, refer to figures 4-1 through 4-5 ). as a result, the instruction execution is stopped, and the handler on the reset vector is executed. the internal status, except some bits of the status registers, is undefined. soft reset C this exception occurs if the reset# (internal) signal is asserted active. as a result, the instruction execution is stopped, and the handler on the reset vector is executed. the internal status before soft reset is retained. however, the current v r 4111 does not support soft reset. nimi C this exception occurs if the nmi (internal) signal is asserted active. tlb refill tlbl/tlbs this exception occurs if there is no tlb entry that matches an address to be referenced in the 32-bit mode. expanded addressing tlb non-coincidence tlbl/tlbs this exception occurs if there is no tlb entry that matches an address to be referenced in the 64-bit mode. tlb invalid tlbl/tlbs this exception occurs if the tlb entry that matches the virtual address to be referenced is invalid (v bit = 0). tlb modify mod this exception occurs if the tlb entry that matches the virtual address to be referenced is valid but is disabled from being written (d bit = 0) when the store instruction is executed. bus error ibe/dbe this exception occurs when the external agent indicates an error of data on the syscmd bus by using an external interrupt to the bus interface (bus time- out, bus parity error, or invalid physical memory address or access type). address error adel/ades this exception occurs if an attempt is made to execute the lh, sh, lw, sw, ld, or sd instruction to the half word/word/double word not located at the half word/word/double word boundary, or if an attempt is made to reference a virtual address that cannot be accessed. integer overflow ov this exception occurs if a 2's complement overflow occurs as a result of addition or subtraction. trap tr this exception occurs if the condition is true as a result of executing the trap instruction. system call sys this exception occurs if the syscall instruction is executed. breakpoint bp this exception occurs if the break instruction is executed. reserved instruction ri this exception occurs if an instruction with an undefined op code (bits 31 to 26) or special instruction with an undefined op code (bits 5 to 0) is executed. coprocessor non-usable cpu this exception occurs if the coprocessor instruction is executed when the corresponding coprocessor enable bit is not set. interrupt int this exception occurs if one of the eight interrupt sources becomes active. cache error C this exception occurs if a parity error is detected in the internal cache or system interface. watch watch this exception occurs if an attempt is made to reference a physical address set by the watch lo/hi register with the load/store instruction. the exception vectors and their offset values in the 64-bit and 32-bit modes are shown below.
data sheet u13211ej2v0ds00 50 m m m m pd30111 table 3-10. base address of exception vector in 64-bit mode (virtual address) vector base address vector offset cold reset, soft reset, nmi 0xffff ffff bfc0 0000 (bev bit is automatically set to 1.) 0x0000 cache error 0xffff ffff a000 0000 (bev = 0) 0xffff ffff bfc0 0200 (bev = 1) 0x0100 tlb refill, exl = 0 0x0000 xtlb refill, exl = 0 0x0080 other than above 0xffff ffff 8000 0000 (bev = 0) 0xffff ffff bfc0 0200 (bev = 1) 0x0180 table 3-11. base address of exception vector in 32-bit mode (virtual address) vector base address vector offset cold reset, soft reset, nmi 0xbfc0 0000 (bev bit is automatically set to 1.) 0x0000 cache error 0xa000 0000 (bev = 0) 0xbfc0 0200 (bev = 1) 0x0100 tlb refill, exl = 0 0x0000 xtlb refill, exl = 0 0x0080 other than above 0x8000 0000 (bev = 0) 0xbfc0 0200 (bev = 1) 0x0180
data sheet u13211ej2v0ds00 51 m m m m pd30111 4. initialization interface remark # in a signal name indicates active low. 4.1 reset function the v r 4111 can be reset in the following five ways. for details, refer to the v r 4111 user's manual . 4.1.1 rtc reset assert the rtcrst# pin active on power application. the status of each of the txd/clksel2, rts#/clksel1, dtr#/clksel0, dbus32/gpio48, mips16en, and gpio49 pins is sampled at the rising edge of the rtcrst# signal, and is internally initialized by the v r 4111. rtc reset does not save the status information at all, and completely initializes the internal status of the processor. because the dram does not enter the self-refresh mode, the contents of the dram after rtc reset are not guaranteed. after reset, the processor serves as the master of the system bus, the sequence of the cold reset exception is executed, and accessing the reset vector in the rom space is started. because only part of the internal status of the v r 4111 is reset, completely initialize the processor by software. figure 4-1. rtc reset rtcrst# (input) power (input) mpower (output) coldreset# (internal) poweron (output) reset# (internal) busclk (output) rstout (output) rtc (internal, 32 khz) undefined stable oscillation > 2 s > 32 ms hi-z 350 ms stable oscillation 16 ms > 4 busclk 16 masterclock note undefined pll (internal) note masterclock is the basic clock in the cpu core.
data sheet u13211ej2v0ds00 52 m m m m pd30111 4.1.2 rstsw assert the rstsw# pin active. reset by rstsw initializes all the internal statuses except the rtc timer and the pmu. because the dram does not enter the self-refresh mode, the contents of the dram after rstsw reset are not guaranteed. after reset, the processor serves as the master of the system bus, the sequence of the cold reset exception is executed, and accessing the reset vector in the rom space is started. because only part of the internal status of the v r 4111 is reset, completely initialize the processor by software. figure 4-2. rstsw note masterclock is the basic clock in the cpu core. rstsw# (input) coldreset# (internal) mras (0:3)# (output) ucas#/lcas# (output) l h power (input) mpower (input) reset# (internal) pll (internal) rtc (internal, 32 khz) stable oscillation stable oscillation stable oscillation undefined > 3 rtc 16 ms 16 masterclock note
data sheet u13211ej2v0ds00 53 m m m m pd30111 4.1.3 deadman?s sw the v r 4111 is reset if the deadmans sw is not cleared within a specific time after the deadmans sw was enabled. for the setting of the deadmans sw, see 12. dsu (deadmans sw unit) . reset by deadmans sw initializes all the internal statuses except the rtc timer and pmu. because the dram does not enter the self-refresh mode, the contents of the dram after deadmans sw reset are not guaranteed. after reset, the processor serves as the master of the system bus, the sequence of the cold reset exception is executed, and accessing the reset vector in the rom space is started. because only part of the internal status of the v r 4111 is reset, completely initialize the processor by software. figure 4-3. deadman's sw note masterclock is the basic clock in the cpu core. rstsw# (input) power (input) mpower (output) coldreset# (internal) reset# (internal) pll (internal) rtc (internal, 32 khz) h l h stable oscillation stable oscillation 16 ms 16 masterclock note stable oscillation undefined
data sheet u13211ej2v0ds00 54 m m m m pd30111 4.1.4 software shutdown when the software executes the hibernate instruction, the v r 4111 places the dram in the self-refresh mode, deasserts the mpower pin inactive, and enters the reset status. reset by software shutdown initializes all the internal statuses except the rtc timer and the pmu. after reset, the processor serves as the master of the system bus, the sequence of the cold reset exception is executed, and accessing the reset vector in the rom space is started. because only part of the internal status of the v r 4111 is reset, completely initialize the processor by software. figure 4-4. software shutdown notes 1. wait time until starting. this value can be changed by a setting of the pmuwaitreg register. for details, refer to v r 4111 users manual . 2. masterclock is the basic clock in the cpu core. power (input) poweron (output) mpower (output) coldreset# (internal) reset# (internal) pll (internal) rtc (internal, 32 khz) stable oscillation stable oscillation stop undefined note 1 16 ms 16 masterclock note 2 > 32 ms mras (0:3)#/ ucas#/lcas# (output)
data sheet u13211ej2v0ds00 55 m m m m pd30111 4.1.5 haltimer shutdown the v r 4111 enters the reset status if the haltimer is not cleared (the haltimerrst bit of the pmucntreg register is set to 1) by software within 4 seconds after rtc reset has been cleared. reset by haltimer initializes all the internal statuses except the rtc timer and pmu. after reset, the processor serves as the master of the system bus, the sequence of the cold reset exception is executed, and accessing the reset vector in the rom space is started. because only part of the internal status of the v r 4111 is reset, completely initialize the processor by software. figure 4-5. haltimer shutdown notes 1. wait time until starting. this value can be changed by a setting of the pmuwaitreg register. for details, refer to v r 4111 users manual . 2. masterclock is the basic clock in the cpu core. 4.2 cpu core registers after reset each of the cpu core registers is reset as follows: the ts and sr bits of the status register are cleared to 0. the erl and bev bits of the status register are set to 1. the upper-limit value (31) is set to the random register. the wired register is initialized to 0. bits 31 through 28 of the config register are cleared to 0, and bits 22 through 3 are set to 0x04800. the other bits are undefined. the values of the registers other than above are undefined. power (input) poweron (output) mpower (output) coldreset# (internal) reset# (internal) pll (internal) rtc (internal, 32 khz) stable oscillation stop 4 s > 32 ms note 1 16 ms 16 masterclock note 2 undefined mras (0:3)#/ ucas#/lcas# (output) stable oscillation
data sheet u13211ej2v0ds00 56 m m m m pd30111 4.3 power-on sequence the causes that change the status of the v r 4111 from the hibernate mode or shutdown status to the fullspeed mode are called power-on factors. the power-on factors include asserting the poweron pin active, asserting the dcd# pin active, alarm from the wakeup timer, and asserting the gpio (0:3), gpio (9:12) pins active. when a power-on factor occurs, the v r 4111 asserts the poweron pin active to inform the external circuit that power to the v r 4111 is about to be turned on. three rtc clocks after the poweron pin has been asserted active, the v r 4111 checks the status of the battinh/battint# pin. when the battinh/battint# pin is low, the v r 4111 deasserts the poweron pin inactive one rtc clock after checking the battinh or gpio9 pin status, and is not started. if the battinh/battint# pin is high, the v r 4111 deasserts the poweron pin inactive three rtc clocks after the checking, asserts the mpower pin active, and is started. figure 4-6 shows the timing chart where the v r 4111 is started. figure 4-7 shows the timing chart where the v r 4111 is not started because the battinh/battint# pin is low. figure 4-6. start sequence of v r 4111 (if started) poweron (output) mpower (input) coldreset# (internal) reset# (internal) pll (internal) battinh/battint# (input) rtc (internal, 32 khz) stop detection of power-on factor checks status of battinh/battint# pin cpu starts undefined status stable oscillation
data sheet u13211ej2v0ds00 57 m m m m pd30111 figure 4-7. start sequence of v r 4111 (if not started) poweron (output) mpower (output) coldreset# (internal) reset# (internal) pll (internal) battinh/battint# (input) rtc (internal, 32 khz) detection of power-on factor checks status of battinh/battint# pin cpu does not start l l l h
data sheet u13211ej2v0ds00 58 m m m m pd30111 5. bcu (bus control unit) the bcu transfers data received via the v r 4110 cpu core and sysad bus (internal) inside the v r 4111. it also controls an external lcd controller, dram, rom (flash memory or mask rom), and pcmcia controller via a system bus, and transfers data received via these devices add bus and data bus. for the charts of the timing between the v r 4111 and each external device controlled by the bcu, see 23. electrical specifications . table 5-1. bcu registers physical address symbol function 0x0b00 0000 bcucntreg1 bcu control register 1 0x0b00 0002 bcucntreg2 bcu control register 2 0x0b00 000a bcuspeedreg bcu access cycle c hange register 0x0b00 000c bcuerrstreg bcu bus error status register 0x0b00 000e bcurfcntreg bcu refresh control register 0x0b00 0010 revidreg peripheral unit revision id register 0x0b00 0012 bcurfcountreg bcu refresh cycle c ount register 0x0b00 0014 clkspeedreg clock specify register 0x0b00 0016 bcucntreg3 bcu control register 3
data sheet u13211ej2v0ds00 59 m m m m pd30111 6. dmaau (dma address unit) the dmaau controls the addresses for the dma operations between aiu/irda 4-mbps communication module (fir) and memory. the dma start address of each dma channel can be specified in the range of 0x0000 0000 to 0x01ff fffe as a half-word address. the dma space of each dma channel is secured in a 2-kbyte block that starts from the address generated by masking the lower ten bits of the dma start address to zero. the dma operation is not guaranteed if the dma space overlaps that of other peripheral units. table 6-1. dmaau registers physical address symbol function 0x0b00 0020 aiuibalreg dma base lower address register for aiu input 0x0b00 0022 aiuibahreg dma base higher address register for aiu input 0x0b00 0024 aiuialreg dma lower address register for aiu input 0x0b00 0026 aiuiahreg dma higher address register for aiu input 0x0b00 0028 aiuobalreg dma base lower address register for aiu output 0x0b00 002a aiuobahreg dma base higher address register for aiu output 0x0b00 002c aiuoalreg dma lower address register for aiu output 0x0b00 002e aiuoahreg dma higher address register for aiu output 0x0b00 0030 firbalreg dma base lower address register for fir 0x0b00 0032 firbahreg dma base higher address register for fir 0x0b00 0034 firalreg dma lower address register for fir 0x0b00 0036 firahreg dma higher address register for fir
data sheet u13211ej2v0ds00 60 m m m m pd30111 7. dcu (dma control unit) the dcu controls the dma operation. it controls the dma requests from the internal peripheral i/o units (aiu and fir) and the acknowledge signal from the bcu that performs bus arbitration, and enables or disables the dma operation. table 7-1. dcu registers physical address symbol function 0x0b00 0040 dmarstreg dma reset register 0x0b00 0042 dmaidlereg dma sequencer status register 0x0b00 0044 dmasenreg dma sequencer enable register 0x0b00 0046 dmamskreg dma mask register 0x0b00 0048 dmareqreg dma request register 0x0b00 004a tdreg transfer direction set register
data sheet u13211ej2v0ds00 61 m m m m pd30111 8. cmu (clock mask unit) the cmu is used to specify whether the cpu core supplies the clock to each peripheral unit. by supplying the clock only to the necessary peripheral units, the power consumption can be reduced. table 8-1. cmu register physical address symbol function 0x0b00 0060 cmuclkmsk cmu clock mask register 9. icu (interrupt control unit) the icu receives an interrupt request signal from each peripheral unit and generates an interrupt request signal (int0, int1, int2, int3, or nmi) to the cpu core. table 9-1. icu registers physical address symbol function 0x0b00 0080 sysint1reg system interrupt register 1 (level 1) 0x0b00 0082 piuintreg piu interrupt register (level 2) 0x0b00 0084 aiuintreg aiu interrupt register(level 2) 0x0b00 0086 kiuintreg kiu interrupt register (level 2) 0x0b00 0088 giuintlreg giu interrupt lower address register (level 2) 0x0b00 008a dsiuintreg dsiu interrupt register (level 2) 0x0b00 008c msysint1reg system interrupt mask register 1 (level 1) 0x0b00 008e mpiuintreg piu interrupt mask register (level 2) 0x0b00 0090 maiuintreg aiu interrupt mask register (level 2) 0x0b00 0092 mkiuintreg kiu interrupt mask register (level 2) 0x0b00 0094 mgiuintlreg giu interrupt mask lower address register (level 2) 0x0b00 0096 mdsiuintreg dsiu interrupt mask register (level 2) 0x0b00 0098 nmireg battery interrupt select register 0x0b00 009a softintreg software interrupt register 0x0b00 0200 sysint2reg system interrupt register 2 (level 1) 0x0b00 0202 giuinthreg giu interrupt higher address register (level 2) 0x0b00 0204 firintreg fir interrupt register (level 2) 0x0b00 0206 msysint2reg system interrupt mask register 2 (level 1) 0x0b00 0208 mgiuinthreg giu interrupt mask higher address register (level 2) 0x0b00 020a mfirintreg fir interrupt mask register (level 2)
data sheet u13211ej2v0ds00 62 m m m m pd30111 figure 9-1. icu configuration mfirintreg 5 firintreg 5 softintreg buserrint dozepiuint ledint hspint siuint and/or 7 mdsiuintreg 4 dsiuintreg 4 and/or mgiuintlreg 16 giuintlreg 16 and/or mgiuinthreg 16 giuinthreg 16 and/or mkiuintreg 3 kiuintreg 3 and/or maiuintreg 7 aiuintreg 7 and/or mpiuntreg 6 piuintreg 6 and/or etimerint rtclong1int rtclong2int powerint battint tclkint sysint1reg sysint2reg msysint1reg msysint2reg and/or 17 6 17 nmi (battint note ) int3 (hspint) int2 (rtclong2int) int1 (rtclong1int) int0 (all interrupts except for battint note and rtclongint.) interrupt indication register interrupt mask register and/or logic (checks masking of each bit and summarizes interrupt request of each register.) level 2 level 1 note for battint, whether nmi or int0 is used can be specified by nmireg. if nmi is selected, the cpu core cannot mask this interrupt, however, msysint1reg in the icu can set the mask.
data sheet u13211ej2v0ds00 63 m m m m pd30111 10. pmu (power management unit) the pmu manages and controls power to the internal and external circuits of the v r 4111 as follows: controls shutdown controls reset controls power-on controls low-power consumption mode (power mode) pmu also set the start cause via the gpio (0:3), (9:12) pins and dcd# pin. table 10-1. pmu registers physical address symbol function 0x0b00 00a0 pmuintreg pmu interrupt/status register 0x0b00 00a2 pmucntreg pmu control register 0x0b00 00a4 pmuint2reg pmu interrupt/status register 2 0x0b00 00a6 pmucnt2reg pmu control register 2 0x0b00 00a8 pmuwaitreg pmu wait count register 10.1 power mode the v r 4111 supports the following four power modes: fullspeed mode standby mode suspend mode hibernate mode figure 10-1 illustrates the transition of the power modes. to change the mode from fullspeed to standby, suspend, or hibernate, execute the standby, suspend, or hibernate instruction. to change the mode from standby, suspend, or hibernate to fullspeed, either generate an interrupt, or execute a reset operation. table 10-2 outlines each power mode.
data sheet u13211ej2v0ds00 64 m m m m pd30111 figure 10-1. power mode transition (1) (2) (3) (4) (5) (6) standby instruction, pipeline flash, sysad idle, pclock high level all interrupts suspend instruction, pipeline flash, sysad idle, pclock high level, tclock high level, dram self refresh start power rstsw elapsed time rtclong1 rtclong2 keytouch pentouch gpio (9:14) gpio (0:3) dcd# (gpio, siu) battintr hibernate instruction, pipeline flash, sysad idle, pclock high level, tclock high level, masterout high level, dram self refresh start power elapsed time dcd# gpio (0:3) gpio (9:12) table 10-2. outline of power mode internal peripheral unit mode rtc icu dcu others pipe line fullspeed on on on selectable note on standby on on on selectable note off suspend on on off off off hibernate on off off off off off off off off off off note refer to 8. cmu (clock mask unit) . standby mode suspend mode fullspeed mode hibernate mode (1) (2) (3) (4) (6) (5)
data sheet u13211ej2v0ds00 65 m m m m pd30111 11. rtc (real-time clock unit) the rtc unit consists of the following three types of timers. rtclong timer (two timers) this is a 24-bit programmable down counter that counts down at a cycle of 32.768 khz. it can generate an interrupt request at intervals of up to 512 seconds. elapsedtime timer (one timer) this is a 48-bit up counter that counts up at a cycle of 32.768 khz. when this counter counts up to about 272 years, it returns to 0. this counter consists of an 48-bit comparator (ecmphreg, ecmplreg, ecmpmreg) and a 48-bit alarm time register (etimelreg, etimemreg, etimehreg). by comparing these, an interrupt request can be generated at specific time. tclock count timer (one timer) this is a 25-bit programmable counter that counts down at each tclock cycle. interrupt requests can be generated with a cycle of up to 2 seconds by setting the clksel (0:2) pins. this timer is used for performance evaluation. table 11-1. rtc registers physical address symbol function 0x0b00 00c0 etimelreg elapsed time timer lower register 0x0b00 00c2 etimemreg elapsed time timer middle register 0x0b00 00c4 etimehreg elapsed time timer higher register 0x0b00 00c8 ecmplreg elapsed time timer compare lower register 0x0b00 00ca ecmpmreg elapsed time timer compare middle register 0x0b00 00cc ecmphreg elapsed time timer compare higher register 0x0b00 00d0 rtcl1lreg rtclong 1 timer lower register 0x0b00 00d2 rtcl1hreg rtclong 1 timer higher register 0x0b00 00d4 rtcl1cntlreg rtclong 1 timer count lower register 0x0b00 00d6 rtcl1cnthreg rtclong 1 timer count higher register 0x0b00 00d8 rtcl2lreg rtclong 2 timer lower register 0x0b00 00da rtcl2hreg rtclong 2 timer higher register 0x0b00 00dc rtcl2cntlreg rtclong 2 timer count lower register 0x0b00 00de rtcl2cnthreg rtclong 2 timer count higher register 0x0b00 01c0 tclklreg tclock counter lower register 0x0b00 01c2 tclkhreg tclock counter higher register 0x0b00 01c4 tclkcntlreg tclock counter count lower register 0x0b00 01c6 tclkcnthreg tclock counter count higher register 0x0b00 01ce rtcintreg rtc interrupt register
data sheet u13211ej2v0ds00 66 m m m m pd30111 12. dsu (deadman's sw unit) the dsu automatically detects a runaway of the v r 4111 and resets the v r 4111. by stopping a runaway at the earliest stage by using the dsu, destruction of data can be minimized. the dsu can be set for a cycle of up to 15 seconds in units of 1 second. set the dswclr bit of the dsuclrreg register to 1 within this time by means of software. if the bit is not set within this time, the v r 4111 enters the reset status (refer to 4. initialization interface ). table 12-1. dsu registers physical address symbol function 0x0b00 00e0 dsucntreg dsu control register 0x0b00 00e2 dsusetreg dsu cycle set register 0x0b00 00e4 dsuclrreg dsu clear register 0x0b00 00e6 dsutimreg dsu elapsed time register
data sheet u13211ej2v0ds00 67 m m m m pd30111 13. giu (general-purpose i/o unit) the giu controls the gpio and dcd# pins. the gpio pins constitute a general-purpose i/o port. giu can assign the interrupt request signal function for these pins. as a trigger, the edge of the input signal (rising or falling edge), high level, or low level can be selected. use the pmucntreg register of pmu, however, to specify the power-on factor via the gpio (0:3), gpio (9:12), or dcd# pin. table 13-1. giu registers physical address symbol function 0x0b00 0100 giuiosell gpio input/output setting lower register 0x0b00 0102 giuioselh gpio input/output setting higher register 0x0b00 0104 giupiodl gpio input/output data lower register 0x0b00 0106 giupiodh gpio input/output data higher register 0x0b00 0108 giuintstatl gpio interrupt lower register 0x0b00 010a giuintstath gpio interrupt higher register 0x0b00 010c giuintenl gpio interrupt enable lower register 0x0b00 010e giuintenh gpio interrupt enable higher register 0x0b00 0110 giuinttypl gpio interrupt trigger setting lower register 0x0b00 0112 giuinttyph gpio interrupt trigger setting higher register 0x0b00 0114 giuintalsell gpio interrupt level setting lower register 0x0b00 0116 giuintalselh gpio interrupt level setting higher register 0x0b00 0118 giuinthtsell gpio interrupt hold setting lower register 0x0b00 011a giuinthtselh gpio interrupt hold setting higher register 0x0b00 011c giupodatl gpio output data lower register 0x0b00 011e giupodath gpio output data higher register 0x0b00 02e0 giuuseupdn gpio pull-up/pull-down enable register 0x0b00 02e2 giutermupdn gpio pull-up/pull-down setting register table 13-2. outline of gpio pins pin name interrupt request detection clock (internal) input buffer type gpio (49:32) C C gpio (31:16) tclock normal gpio15 (dcd#) masterout normal gpio (14:9) masterout normal gpio (8:4) tclock schmitt gpio (3:0) rtc schmitt caution pin gpio15 cannot be used as a general-purpose i/o pin because its function is fixed to dcd# signal input.
data sheet u13211ej2v0ds00 68 m m m m pd30111 14. piu (touch panel unit) the piu uses an on-chip 10-bit a/d converter and detects the x and y coordinates of pen contact locations on the touch panel, and scans the general-purpose a/d input port. since the touch panel control circuit and the a/d converter (conversion precision: 10 bits) are both on-chip, the touch panel can be connected directly to the v r 4111. figure 14-1. piu peripheral block diagram table 14-1. piu registers physical address symbol function 0x0b00 0122 piucntreg piu control register 0x0b00 0124 piuintreg piu interrupt register 0x0b00 0126 piusivlreg piu data sampling cycle set register 0x0b00 0128 piustblreg piu a/d converter wait time set register 0x0b00 012a piucmdreg piu a/d command register 0x0b00 0130 piuascnreg piu a/d port scan register 0x0b00 0132 piuamskreg piu a/d scan mask register 0x0b00 013e piucivlreg piu wait time count register 0x0b00 02a0 piupb00reg piu page 0 buffer 0 register 0x0b00 02a2 piupb01reg piu page 0 buffer 1 register 0x0b00 02a4 piupb02reg piu page 0 buffer 2 register 0x0b00 02a6 piupb03reg piu page 0 buffer 3 register 0x0b00 02a8 piupb10reg piu page 1 buffer 0 register 0x0b00 02aa piupb11reg piu page 1 buffer 1 register 0x0b00 02ac piupb12reg piu page 1 buffer 2 register 0x0b00 02ae piupb13reg piu page 1 buffer 3 register 0x0b00 02b0 piuab0reg piu a/d scan buffer 0 register 0x0b00 02b2 piuab1reg piu a/d scan buffer 1 register 0x0b00 02b4 piuab2reg piu a/d scan buffer 2 register 0x0b00 02b6 piuab3reg piu a/d scan buffer 3 register 0x0b00 02bc piupb04reg piu page 0 buffer 4 register 0x0b00 02be piupb14reg piu page 1 buffer 4 register i/o buffer audioin adin2 adin1 adin0 selector 4 i/o buffer tpy1 tpy0 tpx1 tpx0 4 1 adc piu aiu v r 4111 touch panel battery, etc.
data sheet u13211ej2v0ds00 69 m m m m pd30111 15. siu (serial interface unit) the siu is a serial interface that conforms to the rs-232c communication standard and is equipped with two one- channel interfaces, one for transmission and one for reception. the siu is functionally compatible with the ns16550, and supports a transfer rate up to 1.152 mbps. this unit also has an infrared communication function that corresponds to sir. table 15-1. siu registers physical address lcr7 r/w symbol function r siurb receive buffer register (read) 0 w siuth transmission hold register (write) 0x0c00 0000 1 r/w siudll division ratio lower byte register 0 r/w siuie interrupt enable register 0x0c00 0001 1 r/w siudlm division ratio higher byte register r siuiid interrupt identification register (read) 0x0c00 0002 C w siufc fifo control register (write) 0x0c00 0003 C r/w siulc line control register 0x0c00 0004 C r/w siumc modem control register 0x0c00 0005 C r/w siuls line status register 0x0c00 0006 C r/w siums modem status register 0x0c00 0007 C r/w siusc scratch register 0x0c00 0008 C r/w siuirsel serial communication select register 0x0c00 0009 C r/w siureset siu reset register 0x0c00 000a C r/w siucsel siu echo-back control register remark lcr7 is bit 7 of the siulc register.
data sheet u13211ej2v0ds00 70 m m m m pd30111 figure 15-1. siu peripheral block diagram cpu core bcu siu piad piwrdata interrupt request signal (to icu) internal external irdin irdout# irda module rxd txd rs-232c connector siuout control signal (to dcu)
data sheet u13211ej2v0ds00 71 m m m m pd30111 figure 15-2. example of connection between v r 4111 and irda module irdin rxda irdout# txd firdin#/sel rxdb v r 4111 irda module (a) when hp product used irdin rxd irdout# txd firdin#/sel sel v r 4111 irda module (b) when temic product used irdin rxd irdout# txd firdin#/sel v r 4111 irda module (c) when sharp product used nc remark nc: no connection
data sheet u13211ej2v0ds00 72 m m m m pd30111 16. aiu (audio interface unit) the aiu supports speaker output and microphone input operations. it has 10-bit a/d and d/a converters, and functions as the digital voice i/o interface. dma operation is supported for both input and output operations. table 16-1. aiu registers physical address symbol function 0x0b00 0160 mdmadatreg mic input dma data register 0x0b00 0162 sdmadatreg speaker output dma data register 0x0b00 0166 sodatreg speaker output data register 0x0b00 0168 scntreg speaker output control register 0x0b00 016a scnvrreg d/a conversion rate setting register 0x0b00 0170 midatreg mic input data register 0x0b00 0172 mcntreg mic input control register 0x0b00 0174 mcnvrreg a/d conversion rate setting register 0x0b00 0178 dvalidreg data valid indicate register 0x0b00 017a seqreg sequencer operation enable register 0x0b00 017c intreg aiu interrupt register
data sheet u13211ej2v0ds00 73 m m m m pd30111 17. kiu (keyboard interface unit) the kiu includes 12 scan lines and 8 detection lines to enable detection when 64, 80, or 96 keys are pressed. the number of scan lines can be selected from 8, 10, and 12. the 12 scan lines can be used as a general-purpose output port by setting the following registers. table 17-1. kiu registers physical address symbol function 0x0b00 0180 kiudat0 kiu data 0 register 0x0b00 0182 kiudat1 kiu data 1 register 0x0b00 0184 kiudat2 kiu data 2 register 0x0b00 0186 kiudat3 kiu data 3 register 0x0b00 0188 kiudat4 kiu data 4 register 0x0b00 018a kiudat5 kiu data 5 register 0x0b00 0190 kiuscanrep kiu key scan control register 0x0b00 0192 kiuscans kiu sequencer status register 0x0b00 0194 kiuwks kiu key scan wait time setting register 0x0b00 0196 kiuwki kiu key scan interval setting register 0x0b00 0198 kiuint kiu interrupt register 0x0b00 019a kiurst kiu reset register 0x0b00 019c kiugpen kiu general-purpose output enable register 0x0b00 019e scanline kiu scan line control register
data sheet u13211ej2v0ds00 74 m m m m pd30111 18. dsiu (debug serial interface unit) the dsiu is a dedicated serial interface unit that is used during debugging. it supports a data transfer rate of up to 115.2 kbps. in addition to the ddin and ddout i/o pins, it supports the dcts# and drts# pins that are used for hardware flow control. these pins can be used as a general-purpose output port when the dsiu is not used. table 18-1. dsiu registers physical address symbol function 0x0b00 01a0 portreg general-purpose port switch register 0x0b00 01a2 modemreg modem control register 0x0b00 01a4 asim00reg asynchronous mode 0 register 0x0b00 01a6 asim01reg asynchronous mode 1 register 0x0b00 01a8 rxb0rreg extend receive buffer register 0x0b00 01aa rxb0lreg receive buffer register 0x0b00 01ac txs0rreg extend transmit shift register 0x0b00 01ae txs0lreg transmit shift register 0x0b00 01b0 asis0reg communication state register 0x0b00 01b2 intr0reg dsiu interrupt register 0x0b00 01b6 bprm0reg baud rate generator prescaler mode register 0x0b00 01b8 dsiuresetreg dsiu reset register
data sheet u13211ej2v0ds00 75 m m m m pd30111 19. led (led control unit) led switches leds on and off at a regular interval. this operation can be executed in standby, suspend, or hibernate mode, and the interval time can be programmed. table 19-1. led registers physical address symbol function 0x0b00 0240 ledhtsreg led on time setting register 0x0b00 0242 ledltsreg led off time setting register 0x0b00 0248 ledcntreg led control register 0x0b00 024a ledastcreg led auto stop time setting register 0x0b00 024c ledintreg led interrupt register
data sheet u13211ej2v0ds00 76 m m m m pd30111 20. hsp (modem interface unit) hsp interfaces between the modem software of the cpu core and the external circuits. this unit uses pc-tels nec56k, and it has the following main functions. controls codec devices and performs serial/parallel conversion of codec transmitted/received data controls signal lines in the data access arrangement block (daa), such as relay or hook table 20-1. hsp registers physical address r/w symbol function 0x0c00 0020 r/w hspinit hsp initialization register 0x0c00 0022 r/w hspdata (7:0) hsp data register (lower) 0x0c00 0023 r/w hspdata (15:8) hsp data register (higher) 0x0c00 0024 w hspindex hsp index register 0x0c00 0028 r hspid (7:0) hsp id register r hsppcs (7:0) hsp i/o address program confirmation register 0x0c00 0029 w hsppctel (7:0) hsp signature check port figure 20-1. block connection example iring ilcsense offhook telcon sdo hspmclk aferst# txan txap rxa hc0 codec fs sdi hspsclk mute daa v r 4111 (hsp) 3 4 speaker lines
data sheet u13211ej2v0ds00 77 m m m m pd30111 21. fir (fast irda interface unit) fir supports the irda 1.1 high-speed infrared communication physical layer standard. for infrared communication corresponding to irda 1.0, use the siu instead. however, the pins interfacing the irda module are common pins. table 21-1. fir registers physical address symbol function 0x0c00 0040 frstr fir reset register 0x0c00 0042 dpintr dma page interrupt register 0x0c00 0044 dpcntr dma page control register 0x0c00 0050 tdr transmitted data register 0x0c00 0052 rdr received data register 0x0c00 0054 imr interrupt mask register 0x0c00 0056 fsr fifo set-up register 0x0c00 0058 irsr1 ir set-up register 1 0x0c00 005c crcsr crc set-up register 0x0c00 005e fircr fir control register 0x0c00 0060 mircr mir control register 0x0c00 0062 dmacr dma control register 0x0c00 0064 dmaer dma enable register 0x0c00 0066 txir transmission indication register 0x0c00 0068 rxir reception indication register 0x0c00 006a ifr interrupt flag register 0x0c00 006c rxsts reception status register 0x0c00 006e txfl transmission frame length register 0x0c00 0070 mrxf maximum reception flame length register 0x0c00 0074 rxfl reception frame length register
data sheet u13211ej2v0ds00 78 m m m m pd30111 22. instruction set the v r 4111 has two types of instructions: 32-bit instructions (mips iii) and 16-bit instructions (mips16). 22.1 mips iii instruction each instruction of the mips iii consists of 1 word (32 bits) located at a word boundary. three instruction formats are available as shown in figure 22-1. by employing the three simplified instruction formats, the decoding of instructions is simplified. complicated operations and addressing modes that are not frequently used are realized by the compiler. 22.1.1 instruction formats the instruction formats of the mips iii are shown below. figure 22-1. mips iii cpu instruction format op 6-bit instruction code rs 5-bit source register number rt 5-bit target (source/destination) register number, or branch condition immediate 16-bit immediate value, branch displacement, or address displacement target 26-bit unconditional branch target address rd 5-bit destination register number sa 5-bit shift funct 6-bit function field 22.1.2 mips iii instruction set list all the mips iii instructions of the v r 4111 are classified into three sets: the instruction set common to all the v r series processors (isa: instruction set architecture), the instruction set executed by the v r 4000 tm series (extended isa), and the system control coprocessor instruction set. each instruction set is listed below. 31 26 25 21 20 16 15 0 op rs rt immediate op target op rs rt rd sa funct 31 26 25 0 31 26 25 21 20 16 15 0 11 10 6 5 i-type (immediate) j-type (jump) r-type (register)
data sheet u13211ej2v0ds00 79 m m m m pd30111 table 22-1. cpu instruction set: isa (1/3) instruction description format load/store instruction op base rt offset lb lbu lh lhu lw lwl lwr sb sh sw swl swr load byte load byte unsigned load halfword load halfword unsigned load word load word left load word right store byte store halfword store word store word left store word right lb rt, offset (base) lbu rt, offset (base) lh rt, offset (base) lhu rt, offset (base) lw rt, offset (base) lwl rt, offset (base) lwr rt, offset (base) sb rt, offset (base) sh rt, offset (base) sw rt, offset (base) swl rt, offset (base) swr rt, offset (base) aiu immediate instruction op rs rt offset addi addiu slti sltiu andi ori xori lui add immediate add immediate unsigned set on less than immediate set on less than immediate unsigned and immediate or immediate exclusive or immediate load upper immediate addi rt, rs, immediate addiu rt, rs, immediate slti rt, rs, immediate sltiu rt, rs, immediate andi rt, rs, immediate ori rt, rs, immediate xori rt, rs, immediate lui rt, rs, immediate 3-operand type instruction op rs rt rd sa funct add addu sub subu slt sltu and or xor nor add add unsigned subtract subtract unsigned set on less than set on less than unsigned and or exclusive or nor add rd, rs, rt addu rd, rs, rt sub rd, rs, rt subu rd, rs, rt slt rd, rs, rt sltu rd, rs, rt and rd, rs, rt or rd, rs, rt xor rd, rs, rt nor rd, rs, rt shift instruction op rs rt rd sa funct sll srl sra sllv srlv srav shift left logical shift right logical shift right arithmetic shift left logical variable shift right logical variable shift right arithmetic variable sll rd, rt, sa srl rd, rt, sa sra rd, rt, sa sllv rd, rt, rs srlv rd, rt, rs srav rd, rt, rs
data sheet u13211ej2v0ds00 80 m m m m pd30111 table 22-1. cpu instruction set: isa (2/3) instruction description format multiplication/division instruction op rs rt rd sa funct mult multu div divu mfhi mflo mthi mtlo multiply multiply unsigned divide divide unsigned move from hi move from lo move to hi move to lo mult rs, rt multu rs, rt div rs, rt divu rs, rt mfhi rd mflo rd mthi rs mtlo rs jump instruction (1) op target j jal jump jump and link j target jal target jump instruction (2) op rs rt rd sa funct jr jalr jump register jump and link register jr rs jalr rs, rd branch instruction (1) op rs rt offset beq bne blez bgtz branch on equal branch on not equal branch on less than or equal to zero branch on greater than zero beq rs, rt, offset bne rs, rt, offset blez rs, offset bgtz rs, offset branch instruction (2) regimm rs sub offset bltz bgez bltzal bgezal branch on less than zero branch on greater than or equal to zero branch on less than zero and link branch on greater than or equal to zero and link bltz rs, offset bgez rs, offset bltzal rs, offset bgezal rs, offset special instruction special rs rt rd sa funct sync syscall break synchronize system call breakpoint sync syscall break coprocessor instruction (1) op rs rt rd sa funct lwcz swcz load word to coprocessor z store word from coprocessor z lwcz rt, offset (base) swcz rt, offset (base) coprocessor instruction (2) op rs rt rd sa funct mtcz mfcz ctcz cfcz move to coprocessor z move from coprocessor z move control to coprocessor z move control from coprocessor z mtcz rt, rd mfcz rt, rd ctcz rt, rd cfcz rt, rd
data sheet u13211ej2v0ds00 81 m m m m pd30111 table 22-1. cpu instruction set: isa (3/3) instruction description format coprocessor instruction (3) copz co cofun copz coprocessor z operation copz cofun coprocessor instruction (4) copz bc br offset bczt bczf branch on coprocessor z true branch on coprocessor z false bczt offset bczf offset table 22-2. cpu instruction set: extended isa (1/2) instruction description format load/store instruction op base rt offset ld ldl ldr lwu sd sdl sdr load doubleword load doubleword left load doubleword right load word unsigned store doubleword store doubleword left store doubleword right ld rt, offset (base) ldl rt, offset (base) ldr rt, offset (base) lwu rt, offset (base) sd rt, offset (base) sdl rt, offset (base) sdr rt, offset (base) aiu immediate instruction op rs rt immediate daddi daddiu doubleword add immediate doubleword add immediate unsigned daddi rt, rs, immediate daddiu rt, rs, immediate 3-operand type instruction op rs rt rd sa funct dadd daddu dsub dsubu doubleword add doubleword add unsigned doubleword subtract doubleword subtract unsigned dadd rd, rs, rt daddu rd, rs, rt dsub rd, rs, rt dsubu rd, rs, rt shift instruction op rs rt rd sa funct dsll dsrl dsra dsllv dsrlv dsrav dsll32 dsrl32 dsra32 doubleword shift left logical doubleword shift right logical doubleword shift right arithmetic doubleword shift left logical variable doubleword shift right logical variable doubleword shift right arithmetic variable doubleword shift left logical+32 doubleword shift right logical+32 doubleword shift right arithmetic+32 dsll rd, rt, sa dsrl rd, rt, sa dsra rd, rt, sa dsllv rd, rt, sa dsrlv rd, rt, sa dsrav rd, rt, sa dsll32 rd, rt, sa dsrl32 rd, rt, sa dsra32 rd, rt, sa multiplication/division instruction (1) op rs rt rd sa funct dmult dmultu ddiv ddivu doubleword multiply doubleword multiply unsigned doubleword divide doubleword divide unsigned dmult rs, rt dmultu rs, rt ddiv rs, rt ddivu rs, rt
data sheet u13211ej2v0ds00 82 m m m m pd30111 table 22-2. cpu instruction set: extended isa (2/2) instruction description format multiplication/division instruction (2) op rs rt immediate madd16 dmadd16 multiply and add 16-bit integer doubleword multiply and add 16-bit integer madd16 rs, rt dmadd16 rs, rt jump instruction op target jalx jump and link exchange jalx target branch instruction (1) op rs rt offset beql bnel blezl bgtzl branch on equal likely branch on not equal likely branch on less than or equal to zero likely branch on greater than zero likely beql rs, rt, offset bnel rs, rt, offset blezl rs, offset bgtzl rs, offset branch instruction (2) regimm rs sub offset bltzl bgezl bltzall bgezall branch on less than zero likely branch on greater than or equal to zero likely branch on less than zero and link likely branch on greater than or equal to zero and link likely bltzl rs, offset bgezl rs, offset bltzall rs, offset bgezall rs, offset exception instruction special rs rt rd sa funct tge tgeu tlt tltu teq tne trap if greater than or equal trap if greater than or equal unsigned trap if less than trap if less than unsigned trap if equal trap if not equal tge rs, rt tgeu rs, rt tlt rs, rt tltu rs, rt teq rs, rt tne rs, rt exception immediate instruction regimm rs sub immediate tgei tgeiu tlti tltiu teqi tnei trap if greater than or equal immediate trap if greater than or equal immediate unsigned trap if less than immediate trap if less than immediate unsigned trap if equal immediate trap if not equal immediate tgei rs, immediate tgeiu rs, immediate tlti rs, immediate tltiu rs, immediate teqi rs, immediate tnei rs, immediate
data sheet u13211ej2v0ds00 83 m m m m pd30111 table 22-3. system control coprocessor (cp0) instruction set instruction description format system control coprocessor instruction (1) cop0 sub rt rd 0 mfc0 mtc0 dmfc0 dmtc0 move from coprocessor 0 move to coprocessor 0 doubleword move from coprocessor 0 doubleword move to coprocessor 0 mfc0 rt, rd mtc0 rt, rd dmfc0 rt, rd dmtc0 rt, rd system control coprocessor instruction (2) cop0 co funct tlbr tlbwi tlbwr tlbp eret read indexed tlb entry write indexed tlb entry write random tlb entry probe tlb for matching entry exception return tlbr tlbwi tlbwr tlbp eret system control coprocessor instruction (3) cop0 co funct standby suspend hibernate standby suspend hibernate standby suspend hibernate system control coprocessor instruction (4) cache base sub offset cache cache operation cache sub, offset (base) 22.1.3 instruction execution time in principle, the v r 4111 executes one instruction in one cycle, but some instructions take two cycles or more. (1) the data loaded by a load instruction cannot be used in the delay slot. if an instruction that uses load data is placed in the delay slot, the pipeline stalls. a store instruction stalls by the delay slot if it is followed by a load instruction or mfc0. if a branch instruction whose condition is satisfied or a jump instruction is executed, the instruction at the destination address is executed after the delay slot. table 22-4. number of delay slot cycles instruction category necessary number of cycles (pcycle) load 1 store 1 jump 1 branch 1
data sheet u13211ej2v0ds00 84 m m m m pd30111 (2) the number of cycles indicated in the table below is necessary for executing an integer multiplication/division or sum-of-products operation instructions. these instructions can be executed in parallel with other instructions, except those that access the hi/lo registers that store the result of an operation, and multiplication/division or sum-of-products operation instructions. table 22-5. number of execution cycles of integer multiplication/division instructions instruction category necessary number of cycles (pcycle) mult 1 multu 1 div 35 divu 35 dmult 4 dmultu 4 ddiv 67 ddivu 67 madd16 1 dmadd16 1 22.2 mips16 instruction mips16 instructions are 16 bits long and located at a half-word boundary. therefore, instruction that is extended by the extend instruction with immediate, and the jal and jalx instructions are 32 bits long. there are 13 types of instruction formats available as shown in figure 22-2. whether execution of the mips16 instructions is enabled or disabled is specified by the mips16en pin on power application, and is indicated by config register cp0. figure 22-2 shows the formats of the mips16 instructions, and table 22-6 lists the mips16 instruction set.
data sheet u13211ej2v0ds00 85 m m m m pd30111 figure 22-2. mips16 instruction format 0 0 11 10 15 0 11 10 8 7 15 0 11 10 8 7 5 4 15 0 11 10 8 7 5 4 15 0 11 10 8 7 5 4 2 1 15 0 11 10 8 7 5 4 2 1 15 0 11 10 8 7 15 0 11 10 8 7 5 4 3 15 0 11 10 8 7 5 4 15 0 11 10 8 7 4 3 15 0 11 10 8 7 15 0 11 10 8 7 5 4 15 0 27 26 25 16 15 21 20 31 op immediate op rx op rx ry funct rri rx ry immediate immediate rrr rx ry rz f rrr-a rx ry f immediate shift rx ry shamt f i8 funct immediate i64 funct immediate i64 funct ry immediate immediate 15:0 immediate 25:21 immediate 20:16 jal x i8 funct r32[4:0] ry i8 funct rz r32[2:0, 4:3] i-type ri-type rr-type rri-type rrr-type rri-a-type shift-type i8-type i8_movr32-type i8_mov32r-type i64-type ri64-type jal, jalx-type op 5-bit major operation code rx 3-bit source/destination register specification ry 3-bit source/destination register specification rz 3-bit source/destination register specification immediate or imm 4-bit, 5-bit, 8-bit, or 11-bit immediate value, branch displacement, or address displacement funct or f function field shamt 3-bit shift quantity
data sheet u13211ej2v0ds00 86 m m m m pd30111 table 22-6. mips16 instruction set (1/2) instruction description format load/store instructions lb lbu lh lhu lw lwu ld sb sh sw sd load bye load byte unsigned load haifword load halfword unsigned load word load word unsigned load doubleword store byte store halfword store word store doubleword lb ry, offset (rx) lbu ry, offset (rx) lh ry, offset (rx) lhu ry, offset (rx) lw ry, offset (rx) lw rx, offset (pc) lw rx, offset (sp) lwu ry, offset (rx) ld ry, offset (rx) ld ry, offset (pc) ld ry, offset (sp) sb ry, offset (rx) sh ry, offset (rx) sw ry, offset (rx) sw rx, offset (sp) sw ra, offset (sp) sd ry, offset (rx) sd ry, offset (sp) sd ra, offset (sp) alu immediate instructions li addiu daddiu slti sltiu cmpi load immediate add immediate unsigned doubleword add immediate unsigned set on less than immediate set on less than immediate unsigned compare immediate li rx, immediate addiu ry, rx, immediate addiu rx, immediate addiu sp, immediate addiu rx, pc, immediate addiu rx, sp, immediate daddiu ry, rx, immediate daddiu ry, immediate daddiu ry, pc, immediate daddiu ry, sp, immediate daddiu sp, immediate slti rx, immediate sltiu rx, immediate cmpi rx, immediate 2-/3-operand type instructions addu subu daddu dsubu slt sltu cmp neg and or xor not move add unsigned subtract unsigned doubleword add unsigned doubleword subtract unsigned set on less than set on less than unsigned compare negate and or exclusive or not move addu rz, rx, ry subu rz, rx, ry daddu rz, rx, ry dsubu rz, rx, ry slt rx, ry sltu rx, ry cmp rx, ry neg rx, ry and rx, ry or rx, ry xor rx, ry not rx, ry move ry, r32 move r32,rz
data sheet u13211ej2v0ds00 87 m m m m pd30111 table 22-6. mips16 instruction set (2/2) instruction description format special instructions extend break extend breakpoint extend break immediate multiplication/division instructions mult multu div divu mfhi mflo dmult dmultu ddiv ddivu multiply multiply unsigned divide divide unsigned move from hi move from lo doubleword multiply doubleword multiply unsigned doubleword divide doubleword divide unsigned mult rx, ry multu rx, ry div rx, ry divu rx, ry mfhi rx mflo rx dmult rx, ry dmultu rx, ry ddlv rx, ry ddivu rx, ry jump/branch instructions jal jalx jr jalr beqz bnez bteqz btnez b jump and link jump and link exchange jump register jump and link register branch on equal to zero branch on not equal to zero branch on t equal to zero branch on t not equal to zero branch unconditional jal target jalx target jr rx jr ra jalr ra, rx beqz rx, immediate bnez rx, immediate bteqz immediate btnez immediate b immediate shift instructions sll srl sra sllv srlv srav dsll dsrl dsra dsllv dsrlv dsrav shift left logical shift right logical shift right arithmetic shift left logical variable shift right logical variable shift right arithmetic variable doubleword shift left logical doubleword shift right logical doubleword shift right arithmetic doubleword shift left logical variable doubleword shift right logical variable doubleword shift right arithmetic variable sll rx, ry, immediate srl rx, ry, immediate sra rx, ry, immediate sllv ry, rx srlv ry, rx srav ry, rx dsll rx, ry, immediate dsrl ry, immediate dsra ry, immediate dsllv ry, rx dsrlv ry, rx dsrav ry, rx
data sheet u13211ej2v0ds00 88 m m m m pd30111 23. electrical specifications absolute maximum ratings (t a = 25 c) parameter symbol condition rating unit v dd2 2.5 v (v dd p, v dd pd, v dd 2) - 0.5 to +3.6 v supply voltage v dd3 3.3 v (cv dd , dv dd , av dd , piuv dd , v dd 3) - 0.5 to +4.0 v v dd3 3 3.7 v - 0.5 to +4.0 v input voltage v i v dd3 < 3.7 v - 0.5 to v dd3 + 0.3 v storage temperature t stg - 65 to +150 c cautions 1. do not short-circuit two or more output pins simultaneously. 2. product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. the specifications and conditions shown in dc characteristics and ac characteristics are the ranges for normal operation and quality assurance of the product. 3. v i can be - 1.5 v if the input pulse is less than 10 ns. operating conditions parameter symbol condition min. max. unit v dd2 2.5 v (v dd p, v dd pd, v dd 2) 2.3 2.7 v supply voltage v dd3 3.5 v (cv dd , dv dd , av dd , piuv dd , v dd 3) 3.0 3.6 v ambient temperature t a - 10 +70 c oscillation start voltage note 1 v dds 3.0 v oscillation hold voltage note 2 v ddh1 2.5 v oscillation hold voltage note 3 v ddh2 3.0 v notes 1. this is a voltage at which oscillation is always started after power application, and is applied to oscillators of 32.768 khz and 18.432 mhz. 2. this is a voltage at which oscillation can be guaranteed if the voltage is lowered from the normal operation level, and is applied to an oscillator of 32.768 khz. 3. this is a voltage at which oscillation can be guaranteed if the voltage is lowered from the normal operation level, and is applied to an oscillator of 18.432 mhz. capacitance (t a = 25 c, v dd = 0 v) parameter symbol condition min. max. unit input capacitance c i 10 pf i/o capacitance c io f c = 1 mhz unmeasured pins returned to 0 v. 10 pf
data sheet u13211ej2v0ds00 89 m m m m pd30111 dc characteristics (t a = - - - - 10 to +70 c, v dd2 = 2.3 to 2.7 v, v dd3 = 3.0 to 3.6 v) (1/2) parameter symbol condition min. typ. max. unit output voltage, high v oh1 i oh = - 2 ma 0.8v dd3 v output voltage, high note 1 v oh2 i oh = - 12 ma 0.8v dd3 v i ol = 2 ma 0.4 output voltage, low v ol i ol = 20 m a0.1 v i ol = 12 ma 0.4 output voltage, low note 1 v ol2 i ol = 20 m a0.1 v input voltage, high note 2 v ih1 2.0 v dd3 + 0.3 v - 0.3 0.3v dd3 v input voltage, low note 2 v il1 pulse less than 10 ns - 1.5 0.3v dd3 v input voltage, high note 3 v ih2 0.75v dd3 v dd3 + 0.3 v - 0.3 0.6 v input voltage, low note 3 v il2 pulse less than 10 ns - 1.5 0.6 v hysteresis voltage note 4 v h 0.17v dd3 v input leakage current note 5 i li v dd3 = 3.6 v, v i = v dd3 , 0 v 5 m a input leakage current, high note 6 i lih v dd3 = 3.6 v, v i = v dd3 36 m a input leakage current, low note 7 i lil v dd3 = 3.6 v, v i = 0 v - 36 m a output leakage current i lo v dd3 = 3.6 v, v i = v dd3 , 0 v 5 m a notes 1. applied to tpx (0:1), tpy (0:1). a panel resistance of 250 w is presumed. 2. except rtcx1, clkx1, firclk, hspsclk, tpx (0:1), tpy (0:1), adin (0:2), audioin, power, rstsw#, rtcrst#, dcd#/gpio15, gpio (0:14), battinh/battint#, iring, and kport (0:7) pins. 3. applied to power, rstsw#, rtcrst#, dcd#/gpio15, gpio (0:14), battinh/battint#, iring, and kport (0:7) pins. 4. hysteresis voltage: difference between the minimum voltage at which the high level of a schmitt input signal is not recognized when the signal goes from low to high and the maximum voltage at which the low level is not recognized when the signal goes from high to low. 5. except kport (0:7) (input pins with pull-down resistor). 6. applied to kport (0:7) (input pins with pull-down resistor) and gpio (0:14) when the internal pull-down resistor is used. 7. applied to gpio (0:14) when the internal pull-up resistor is used.
data sheet u13211ej2v0ds00 90 m m m m pd30111 (2/2) parameter symbol condition min. typ. note 1 max. unit in fullspeed mode 60 140 ma in standby mode 27 49 ma in suspend mode 6 18 ma i dd2 note 2 in hibernate mode, v dd2 = 0.0 v, when led unit is off. 0 m a in fullspeed mode, add (0:25), rd#, wr#, tpx (0:1), tpy (0:1) = 120 pf, other pins = 40 pf 20 45 ma in standby mode, external load 0 pf 6 12 ma in suspend mode, external load 0 pf 0.5 2 ma in hibernate mode, external load 0 pf, when led unit is off. 550 m a power supply current i dd3 note 3 in hibernate mode, external load 0 pf, v dd3 = 2.5 v, when led unit is off. 530 m a notes 1. unless otherwise specified, these are reference values at t a = 25 c, v dd2 = 2.5 v, v dd3 = 3.3 v. 2. total current flowing to the v dd p, v dd pd, and v dd2 pins. 3. total current flowing to the cv dd , dv dd , av dd , piuv dd , and v dd 3 pins. remark i dd2 and i dd3 do not reach the maximum value at the same time in the fullspeed mode.
data sheet u13211ej2v0ds00 91 m m m m pd30111 data retention characteristics (t a = 25 c) parameter symbol condition min. max. unit data retention voltage note 1 v dddr3 hibernate mode, 3.3-v power supply 2.5 3.6 v data retention input voltage, high note 2 v ihdr 0.9v dddr3 v notes 1. the data retention voltage is the voltage at which the operation of the elapsed time timer and the data retention of the registers of the following peripheral units are guaranteed, and is not applied to the internal data of the cpu core. bcu: bcurfcntreg, bcucntreg3 pum: pmucntreg (15:8), pmucnt2reg, pmuwaitreg rtc: etimelreg, etimemreg, etimehreg, ecmplreg, ecmpmreg, ecmphreg, rtcl1lreg, rtcl1hreg, rtcl1cntlreg, rtcl1cnthreg, rtcl2lreg, rtcl2hreg, rtcl2cntlreg, rtcl2cnthreg, rtcintreg (2:0) giu: giupodatl, giupodath, giuuseupnl, giutermupnl kiu: kiugpen, portreg led: ledhtsreg, ledltsreg, ledhltclreg, ledhltchreg, ledcntreg 2. applied to rtcrst# pin. remark the values in parentheses are the targeted values. v dd rtcrst# (input) v ihdr 3.0 v v dddr3
data sheet u13211ej2v0ds00 92 m m m m pd30111 ac characteristics (t a = - - - - 10 to +70 c, v dd2 = 2.3 to 2.7 v, v dd3 = 3.0 to 3.6 v) ac test input waveform (a) cts#, data (0:15), data (16:31)/gpio (16:31), dbus32/gpio48, dcts#/gpio47, ddin/gpio45, dsr#, dtr#/clksel0, fs, firdin#/sel, gpio49, hldrq#, ilcsense, iochrdy, iocs16#, irdin, lcdrdy, memcs16#, rxd, rts#/clksel1, sdi, txd/clksel2, zws# (b) battinh/battint#, dcd#/gpio15, gpio (0:14), iring, kport (0:7), power, rstsw#, rtcrst# ac test output measuring points (c) add (0:25), aferst#, busclk, gpio49, data (0:15), data (16:31)/gpio (16:31), dbus32/gpio48, dcts#/gpio47, ddin/gpio45, ddout/gpio44, drts#/gpio46, dtr#/clksel0, firdin#/sel, gpio (0:14), gpio49, hc0, hldack#, hspmclk, ior#, iow#, irdout#, kscan (0:11)/gpio (32:43), lcas#, lcdcs#, ledout#, memr#, memw#, mpower, mras (0:1)#, mute, offhook, opd#, poweron, rd#, romcs (0:3)#, rstout, rts#/clksel1, sdo, shb#, telcon, tpx (0:1), tpy (0:1), txd/clksel2, ucas#, ulcas#/mras2#, uucas#/mras3#, wr# 2.0 v 0.3 v 2.0 v 0.3 v test points v dd 0 v 0.75v dd 0.2v dd 0.75v dd 0.2v dd test points v dd 0 v 0.5v dd 0.5v dd test points v dd 0 v
data sheet u13211ej2v0ds00 93 m m m m pd30111 load condition (a) add (0:25), rd#, wr#, tpx (0:1), tpy (0:1) (b) other output pins dut add (0:25), rd#, wr#, tpx (0:1), tpy (0:1) c l = 120 pf dut output pin (other than those shown in (a)) c l = 40 pf
data sheet u13211ej2v0ds00 94 m m m m pd30111 (1) clock parameter parameter symbol condition min. typ. max. unit hspsclk high-level width t whsh when hsp unit is used 40 ns hspsclk low-level width t whsl when hsp unit is used 40 ns hspsclk clock frequency t hscyc when hsp unit is used f cyc mhz hspsclk clock cycle t cyhs when hsp unit is used 108.5 ns hspsclk clock rise time t hsr when hsp unit is used 10 ns hspsclk clock fall time t shf when hsp unit is used 10 ns hspmclk high-level width t mph when hsp unit is used t cyhm 0.45 t cyhm 0.55 ns hspmclk low-level width t mpl when hsp unit is used t cyhm 0.45 t cyhm 0.55 ns hspmclk clock frequency t mcyc when hsp unit is used 0.585 18.432 mhz hspmclk clock cycle t cyhm when hsp unit is used 54.253 1790.365 ns busclk high-level width t bclkh 45 ns busclk low-level width t bclkl 45 ns t fircyc1 in fir 4 mbps 47.996 48.000 48.005 mhz firclk input frequency note 1 t fircyc2 in fir 1.152/0.576 mbps 47.952 48.000 48.048 mhz fir clock duty note 1 t firduty 10 90 % clksel (2:0) = 111 note 2 rfu mhz clksel (2:0) = 110 note 2 rfu mhz clksel (2:0) = 101 note 2 rfu mhz clksel (2:0) = 100 note 2 rfu mhz clksel (2:0) = 011 69.3 mhz clksel (2:0) = 010 65.4 mhz clksel (2:0) = 001 62.0 mhz cpu core operating frequency f pcyc clksel (2:0) = 000 49.1 mhz notes 1. applied to firclk pin. 2. do not set clksel2 to 1. remark clksel (2:0): value set to the txd/clksel2, rts#/clksel1, and dtr#/clksel0 pins after reset. t cyhs t whsh t whsl t mph t mpl t bclkh t bclkl hspmclk (output) hspsclk (input) busclk (output) t hsr t shf t cyhm
data sheet u13211ej2v0ds00 95 m m m m pd30111 (2) reset parameter parameter symbol condition min. max. unit reset input low-level width t wrsl rtcrst# pin 305 m s remark for the rtcrst# characteristics at power application, refer to v r 4111 users manual . (3) initialization parameter parameter symbol condition min. max. unit data sampling time (from rtcrst# - ) t ss 61.04 m s output delay time (from rtcrst# - )t od 61.04 m s rtcrst# (input) txd/clksel2 rts#/clksel1 dtr#/clksel0 (i/o) dbus32/gpio48 mips16en gpio49 note (input) hi-z hi-z t ss t od don , t care input sampling output hi-z note be sure to input a low level to gpio49 in this timing. remark set the input data level by using a pull-up or pull-down resistor with high resistance. rtcrst# (input) t wrsl
data sheet u13211ej2v0ds00 96 m m m m pd30111 (4) gpio interface parameter (1/2) parameter symbol condition min. max. unit t inp1 note 1 91.5 m s t inp2 note 2 361.5 ns input level width t inp3 note 3 180.6 ns t gpinr1 note 4 200 ns gpio input rise time t gpinr2 note 5 10 ns t gpinf1 note 4 200 ns gpio input fall time t gpinf2 note 5 10 ns output level width t outp note 6 30 ns notes 1. applied to gpio (0:3) pins. 2. applied to dcd#/gpio15 and gpio (9:14) pins. 3. applied to data (16:31)/gpio (16:31) and gpio (4:8) pins. 4. applied to gpio (0:14) and dcd#/gpio15 pins. 5. applied to data (16:31)/gpio (16:31) pins. 6. applied to gpio (0:14), data (16:31)/gpio (16:31), kscan (0:11)/gpio (32:43), ddout/gpio44, ddin/gpio45, drts#/gpio46, dcts#/gpio47, dbus32/gpio48, and gpio49 pins. caution these parameters are applied when the data (16:31)/gpio (16:31), dcd#/gpio15, kscan (0:11)/gpio (32:43), ddout/gpio44, ddin/gpio45, drts#/gpio46, dcts#/gpio47, dbus32/gpio48, or gpio49 pin is used as the gpio pin.
data sheet u13211ej2v0ds00 97 m m m m pd30111 (4) gpio interface parameter (2/2) (a) input level width (b) gpio input rise/fall time (c) output level width notes 1. 2. 3. gpio (0:3) dcd#/gpio15, gpio (9:14) data (16:31)/gpio (16:31), gpio (4:8) t inp1 t inp2 t inp3 note 1 note 2 note 3 notes 1. 2. dcd#/gpio15, gpio (0:14) data (16:31)/gpio (16:31) t gpinf1 t gpinf2 note 1 note 2 t gpinr1 t gpinr2 note 1 note 2 note gpio (0:14), data (16:31)/gpio (16:31), kscan (0:11)/gpio (32:43), ddout/gpio44, ddin/gpio45, drts#/gpio46, dcts#/gpio47, dbus32/gpio48, gpio49 t outp note
data sheet u13211ej2v0ds00 98 m m m m pd30111 (5) edo-type dram read parameter (1/2) the target dram is the m pd42s16165l-a60, 42s16165l-a70, 42s18165l-a60, 42s18165l-a70, 42s64165g5-a50, 42s64165g5-a60, 42s65165g5-a50, or 42s65165g5-a60. parameter symbol condition min. max. unit mras (0:3)# pulse width t rasp 75 ns mras (0:3)# hold time (from ucas#/lcas# precharge) t rhcp 45 ns mras (0:3)# precharge time t rp 55 ns ucas#/lcas# hold time (from mras (0:3)#) t csh 55 ns ucas#/lcas# pulse width t hcas 12 ns ucas#/lcas# precharge time t cp 10 ns read/write cycle time t hpc 31 ns mras (0:3)# hold time (from ucas#/lcas#) t rsh 20 ns row address setup time (to mras (0:3)#) t asr 0ns ucas#/lcas# delay time from mras (0:3)# t rcd 19 ns column address delay time from mras (0:3)# t rad 17 ns column address setup time (to ucas#/lcas#) t asc 0ns column address read time (to mras (0:3)# - )t ral 40 ns row address hold time (from mras (0:3)# )t rah 15 ns column address hold time 1 (from ucas#/lcas# )t cah1 10 ns column address hold time 2 (from ucas#/lcas# )t cah2 10 ns column address hold time 3 (from ucas#/lcas# )t cah3 10 ns data access time (from ucas#/lcas# precharge) t acp 45 ns data access time (from rd# )t oea 23 ns data input setup time 1 (to ucas#/lcas# )t ds1 0ns data input hold time 1 (from mras (0:3)#) t dh1 6ns data input setup time 2 (to ucas#/lcas# )t ds2 0ns data input hold time 2 (from mras (0:3)#) t dh2 6ns data access time (from mras (0:3)# )t rac 75 ns data access time (from column address) t aa 37 ns data access time (from ucas#/lcas# )t cac 23 ns caution these ratings are applied only when a device operates within the recommended operating condition range and the operating ambient temperature is kept constant. if the power supply voltage or operating ambient temperature changes during dram access, the above ratings are not applied.
data sheet u13211ej2v0ds00 99 m m m m pd30111 (5) edo-type dram read parameter (2/2) notes 1. in 32-bit mode: applied to mras (0:1)# in 16-bit mode: applied to uucas#/mras3#, ulcas#/mras2#, and mras (0:1)# 2. in 32-bit mode: applied to uucas#/mras3#, ulcas#mras2#, ucas#, and lcas# in 16-bit mode: applied to ucas# and lcas# 3. in 32-bit mode: applied to data (16:31)/gpio (16:31) and data (0:15) in 16-bit mode: applied to data (0:15) remark the broken lines indicate high impedance. mras (0:3)# note 1 (output) ucas#/lcas# note 2 (output) add (19:23) (output) add (9:18) (output) rd# (output) data note 3 (i/o) t rasp t rhcp t rp t csh t hcas t rsh t asr t rcd t rad t rah t ral t asc t cah1 t cah2 t acp t oea hi-z invalid invalid hi-z t rac t aa t cac t ds1 t dh1 t ds2 t dh2 t cp t hpc t cah3
data sheet u13211ej2v0ds00 100 m m m m pd30111 (6) edo-type dram write parameter (1/2) the target dram is the m pd42s16165l-a60, 42s16165l-a70, 42s18165l-a60, 42s18165l-a70, 42s64165g5-a50, 42s64165g5-a40, 42s65165g5-a50, or 42s65165g5-a60. parameter symbol condition min. max. unit mras (0:3)# pulse width t rasp 75 ns mras (0:3)# hold time (from ucas#/lcas# precharge) t rhcp 45 ns mras (0:3)# precharge time t rp 55 ns ucas#/lcas# hold time (from mras (0:3)# )t csh 55 ns ucas#/lcas# pulse width t hcas 12 ns ucas#/lcas# precharge time t cp 10 ns read/write cycle time t hpc 31 ns mras (0:3)# hold time (from ucas#/lcas#) t rsh 20 ns row address setup time (to mras (0:3)# )t asr 0ns ucas#/lcas# delay time from mras (0:3)# t rcd 19 ns column address delay time from mras (0:3)# t rad 17 ns column address setup time (to ucas#/lcas# )t asc 0ns column address read time (to mras (0:3)# - )t ral 40 ns row address hold time (from mras (0:3)# )t rah 15 ns column address hold time 1 (from ucas#/lcas# )t cah1 10 ns column address hold time 2 (from ucas#/lcas# )t cah2 10 ns column address hold time 3 (from ucas#/lcas# )t cah3 10 ns wr# setup time t wcs 0ns wr# hold time (from ucas#/lcas# )t wch 15 ns data output setup time t d1 0ns data output hold time t d2 10 ns caution these ratings are applied only when a device operates within the recommended operating condition range and the operating ambient temperature is kept constant. if the power supply voltage or operating ambient temperature changes during dram access, the above ratings are not applied.
data sheet u13211ej2v0ds00 101 m m m m pd30111 (6) edo-type dram write parameter (2/2) notes 1. in 32-bit mode: applied to mras (0:1)# in 16-bit mode: applied to uucas#/mras3#, ulcas#/mras2#, and mras (0:1)# 2. in 32-bit mode: applied to uucas#/mras3#, ulcas#mras2#, ucas#, and lcas# in 16-bit mode: applied to ucas# and lcas# 3. in 32-bit mode: applied to data (16:31)/gpio (16:31) and data (0:15) in 16-bit mode: applied to data (0:15) mras (0:3)# note 1 (output) ucas#/lcas# note 2 (output) add (19:23) (output) add (9:18) (output) wr# (output) data note 3 (i/o) t rasp t rhcp t rp t csh t rsh t hcas t asr t cp t rcd t hpc t cah3 t ral t rad t asc t rah t cah2 t wch t d2 t d1 t d2 t d1 t wcs t cah1 invalid
data sheet u13211ej2v0ds00 102 m m m m pd30111 (7) dram refresh parameter the target dram is the m pd42s161615l-a60, 42s16165l-a70, 42s18165l-a60, 42s18165l-a70, 42s64165g5-a50, 42s64165g5-a60, 42s65165g5-a50, or 42s65165g5-a60. (a) cas-before-ras refresh parameter parameter symbol condition min. max. unit read/write cycle time t rc 124 ns mras (0:3)# pulse width t ras 70 ns mras (0:3)# precharge time t rp 50 ns ucas#/lcas# setup time (to mras (0:3)# )t csr 5ns ucas#/lcas# hold time (from mras (0:3)# )t chr 10 ns mras (0:3)# precharge time from ucas#/lcas# - t crp 5ns ucas#/lcas# precharge time t cpn 10 ns notes 1. in 32-bit mode: applied to mras (0:1)# in 16-bit mode: applied to uucas#/mras3#, ulcas#/mras2#, and mras (0:1)# 2. in 32-bit mode: applied to uucas#/mras3#, ulcas#mras2#, ucas#, and lcas# in 16-bit mode: applied to ucas# and lcas# mras (0:3)# note 1 (output) ucas#/lcas# note 2 (output) wr# (output) h t csr t ras t chr t rp t crp t cpn t rc
data sheet u13211ej2v0ds00 103 m m m m pd30111 (b) cas-before-ras self-refresh parameter parameter symbol condition min. max. unit mras (0:3)# pulse width note t rass 100 m s mras (0:3)# precharge time t rps 130 ns ucas#/lcas# hold time t chs - 50 ns note the cas-before-ras self-refresh parameter is valid when t rass exceeds 100 m s. notes 1. in 32-bit mode: applied to mras (0:1)# in 16-bit mode: applied to uucas#/mras3#, ulcas#/mras2#, and mras (0:1)# 2. in 32-bit mode: applied to uucas#/mras3#, ulcas#mras2#, ucas#, and lcas# in 16-bit mode: applied to ucas# and lcas# mras (0:3)# note 1 (output) ucas#/lcas# note 2 (output) t rass t rps t chs
data sheet u13211ej2v0ds00 104 m m m m pd30111 (8) normal rom parameter (1/2) parameter symbol condition min. max. unit data access time (from address) note t acc t n - 19 ns data access time (from romcs (0:3)# ) note t ce t n - 19 ns data access time (from rd# ) note t oe t (n - 1) - 29 ns data input setup time t ds 0ns data input hold time t dh 6ns note the value of n is set by using the wroma (0:2) bits of the bcuspeedreg register. the value of t is set by using the clksel (0:2) bits (txd/clksel2, rts#/clksel1, and dtr#/clksel0). clksel2 clksel1 clksel0 t (ns) wroma2 wroma1 wroma0 n 1 note 1 note 1 note rfu 0009 1 note 1 note 0 note rfu 0018 1 note 0 note 1 note rfu 0107 1 note 0 note 0 note rfu 0116 01143.3 1005 01045.9 1014 00148.4 1103 00040.7 1112 note do not set clksel2 to 1.
data sheet u13211ej2v0ds00 105 m m m m pd30111 (8) normal rom parameter (2/2) remark the broken lines indicate high impedance. romcs (0:3)# (output) rd# (output) data (i/o) t acc t ce t oe hi-z invalid invalid t ds t dh hi-z add (19:23), add (0:8) (output) add (9:18) (output) note when wroma (0:2) = 111 note in 32-bit mode: applied to data (16:31)/gpio (16:31) and data (0:15) in 16-bit mode: applied to data (0:15)
data sheet u13211ej2v0ds00 106 m m m m pd30111 (9) page rom parameter (1/2) parameter symbol condition min. max. unit data access time (from address) 1 note t acc1 t n - 19 ns data access time (from address) 2 note t acc2 t m - 12 ns data access time (from romcs (0:3)# ) note t ce t n - 19 ns data access time (from rd# ) note t oe t (n - 1) - 29 ns data input setup time t ds 0ns data input hold time t dh 6ns note the value of n is set by using the wroma (0:2) bits of the bcuspeedreg register. the value of m is set by using the wprom (0:1) bits of the bcuspeedreg register. the value of t is set by using the clksel (0:2) bits (txd/clksel2, rts#/clksel1, and dtr#/clksel0). clksel 2 clksel 1 clksel 0 t (ns) wroma 2 wroma 1 wroma 0 n (tclock) wprom 1 wprom 0 m (tclock) 1 note 1 note 1 note rfu 0 0 0 9 0 0 3 1 note 1 note 0 note rfu 0 0 1 8 0 1 2 1 note 0 note 1 note rfu 0 1 0 7 1 0 1 1 note 0 note 0 note rfu 0 1 1 6 1 1 ? 0 1 1 43.3 1 0 0 5 0 1 0 45.9 1 0 1 4 0 0 1 48.4 1 1 0 3 0 0 0 40.7 1 1 1 2 note do not set clksel2 to 1.
data sheet u13211ej2v0ds00 107 m m m m pd30111 (9) page rom parameter (2/2) remark the broken lines indicate high impedance. romcs (0:3)# (output) rd# (output) data (i/o) t acc1 hi-z invalid add (1:3) (output) add (4:23), add0 (output) invalid hi-z t acc2 t ce t oe t ds t dh t ds t dh note note in 32-bit mode: applied to data (16:31)/gpio (16:31) and data (0:15) in 16-bit mode: applied to data (0:15)
data sheet u13211ej2v0ds00 108 m m m m pd30111 (10) flash memory mode write parameter parameter symbol condition min. max. unit write cycle time t avav 150 ns address setup time (to wr# - )t avwh 75 ns address setup time (to romcs (0:3)# )t avel 0ns romcs (0:3)# setup time (to wr# )t elwl 10 ns wr# low-level width t wlwh 75 ns romcs (0:3)# hold time (from wr# - )t wheh 10 ns address hold time (from wr# - )t whax 10 ns wr# high-level width t whwl 75 ns address setup time (to wr# )t avwl 25 ns data output setup time (to wr# - )t dvwh 75 ns data output hold time (from wr# - )t whdx 10 ns romcs (0:3)# (output) wr# (output) invalid add (19:23), add (0:8) (output) add (9:18) (output) t avel t avwl t whwl t wlwh t avwh t avav t dvwh t whdx t elwl t wheh t whax data (i/o) note note in 32-bit mode: applied to data (16:31)/gpio (16:31) and data (0:15) in 16-bit mode: applied to data (0:15)
data sheet u13211ej2v0ds00 109 m m m m pd30111 (11) flash memory mode read parameter parameter symbol condition min. max. unit data output delay time from address t avqv 180 ns data output delay time from romcs (0:3)# t elqv 180 ns address setup time (to romcs (0:3)# )t avel 0ns data output delay time from rd# t glqv 80 ns address setup time (to rd# )t avgl 0ns romcs (0:3)# hold time (from rd# - )t gheh 10 ns address hold time (from rd# - )t ghax 10 ns rd# high-level width t ghgl 75 ns data input setup time t ds 0ns data input hold time t dh 6ns romcs (0:3)# setup time (to rd# )t elgl 10 ns remark the broken lines indicate high impedance. romcs (0:3)# (output) rd# (output) invalid add (19:20), add (0:8) (output) add (9:18) (output) invalid t avel t avgl t elgl t glqv t elqv t alqv t ghgl t gheh t ghax t ds t dh data (i/o) note note in 32-bit mode: applied to data (16:31)/gpio (16:31) and data (0:15) in 16-bit mode: applied to data (0:15) hi-z
data sheet u13211ej2v0ds00 110 m m m m pd30111 (12) system bus parameter (iochrdy) (1/2) parameter symbol condition min. max. unit busclk low-level width t bclkl 45 ns busclk high-level width t bclkh 45 ns address setup time (to busclk) t avck 15 ns address setup time (to command signal ) notes 1, 2 t avcl t n - 29 ns command signal setup time (to busclk) note 1 t clck 15 ns command signal low-level width notes 1, 2 t clch 2 t n - 29 ns address hold time (from command signal - ) note 1 t chav 25 ns command signal recovery time notes 1, 2 t chcl t (n + 1) - 29 ns iochrdy sampling time note 2 t clr 0t n - 44 ns command signal - delay time from iochrdy - notes 1, 2 t rhch t n2 t n + 29 ns iochrdy hold time (from command signal - ) note 1 t chrl 0ns data output setup time (to command signal ) note 1 t dvcl 0ns data output hold time (from command signal - ) note 1 t chdv 25 ns memcs16#/iocs16# sampling start time note 2 t avsv1 2 t n - 44 ns memcs16#/iocs16# hold time (from command signal ) note 1 t chsv 0ns data input setup time t ds 0ns data input hold time t dh 15 ns notes 1. with the v r 4111, the memw#, memr#, iow#, and ior# pins are called the command signals for the system bus interface. 2. the value of n is set by using the wisaa (0:2) bits of the bcuspeedreg register. the value of t is set by using the clksel (0:2) bits (txd/clksel2, rts#/clksel1, and dtr#/clksel0). clksel2 clksel1 clksel0 t (ns) wisaa2 wisaa1 wisaa0 n (tclock) 1 note 1 note 1 note rfu 0008 1 note 1 note 0 note rfu 0017 1 note 0 note 1 note rfu 0106 1 note 0 note 0 note rfu 0115 01143.3 1 note 0 note 0 note 4 01045.9 1 note 0 note 1 note 3 00148.4 110 ? 00040.7 111 ? note do not set clksel2 to 1. note if the wisaa (0:2) bits are set to 100 or high, the ac characteristics of t avck and t clck are not guaranteed.
data sheet u13211ej2v0ds00 111 m m m m pd30111 (12) system bus parameter (iochrdy) (2/2) notes 1. busclk indicates that there are four possible relationships between busclk and other system bus interface signals. 2. this indicates the minimum setup time to the busclk rising or falling edge. remark the broken lines indicate high impedance. hi-z invalid when wisaa (0:2) = 010 busclk note 1 (output) busclk note 1 (output) busclk note 1 (output) busclk note 1 (output) add (19:25), add (0:8) (output) add (9:18) (output) shb# (output) memr#/memw#, ior#/iow# (output) iochrdy (input) zws# (input) data (output) data (input) invalid t bclkh t bclkl t avck note 2 t clck note 2 t clch t chav t chcl t chrl t chdv t dh t ds t rhch t clr t dvcl t avcl invalid memcs16#, iocs16# (input) t chsv t avsv1
data sheet u13211ej2v0ds00 112 m m m m pd30111 (13) system bus parameter (zws#) (1/2) parameter symbol condition min. max. unit address setup time (to busclk) t avck 15 ns address setup time (to command signal ) notes 1, 2 t avcl t n - 29 ns command signal setup time (to busclk) note 1 t clck 15 ns command signal low-level width notes 1, 2 t clch t n - 31 ns address hold time (from command signal - ) note 1 t clav 25 ns command signal recovery time notes 1, 2 t chcl t (n + 1) - 29 ns zws# delay time from command signal notes 1, 2 t clzl t (n - 1) - 20 ns zws# hold time (from command signal - ) note 1 t chzh 0ns data output setup time (to command signal ) note 1 t dvcl 0ns data output hold time (from command signal - ) note 1 t chdv 25 ns memcs16#/iocs16# sampling start time note 2 t avsv2 2 t (n C 1) C 44 ns memcs16#/iocs16# hold time (from command signal - ) note 1 t chsv 0ns data input setup time t ds 0ns data input hold time t dh 15 ns notes 1. with the v r 4111, the memw#, memr#, iow#, and ior# pins are called the command signals for the system bus interface. 2. the value of n is set by using the wisaa (0:2) bits of the bcuspeedreg register. the value of t is set by using the clksel (0:2) bits (txd/clksel2, rts#/clksel1, and dtr#/clksel0). clksel2 clksel1 clksel0 t (ns) wisaa2 wisaa1 wisaa0 n (tclock) 1 note 1 note 1 note rfu 0008 1 note 1 note 0 note rfu 0017 1 note 0 note 1 note rfu 0106 1 note 0 note 0 note rfu 0115 01143.3 1 note 0 note 0 note 4 01045.9 1 note 0 note 1 note 3 00148.4 110 ? 00040.7 111 ? note do not set clksel2 to 1. note if the wisaa (0:2) bits are set to 100 or high, the ac characteristics of t clck and t avck are not guaranteed.
data sheet u13211ej2v0ds00 113 m m m m pd30111 (13) system bus parameter (zws#) (2/2) notes 1. busclk indicates that there are four possible relationships between busclk and other system bus interface signals. 2. this indicates the minimum setup time to the busclk rising or falling edge. remark the broken lines indicate high impedance. hi-z invalid when wisaa (0:2) = 101 busclk note 1 (output) busclk note 1 (output) busclk note 1 (output) busclk note 1 (output) add (19:25), add (0:8) (output) add (9:18) (output) shb# (output) memr#/memw#, ior#/iow# (output) iochrdy (input) zws# (input) data (output) data (input) invalid t avck note 2 t clck note 2 t clck t clav t chcl t chdv t dh t ds t dvcl t avcl invalid t clzl t chzh memcs16#, iocs16# (input) t chsv t avsv2
data sheet u13211ej2v0ds00 114 m m m m pd30111 (14) high-speed system bus parameter (iochrdy) (1/2) parameter symbol condition min. max. unit address setup time (to command signal ) notes 1, 2 t avcl t n - 29 ns command signal low-level width notes 1, 2 t clch t (n + m) - 29 ns address hold time (from command signal - ) note 1 t chav 25 ns command signal recovery time notes 1, 2 t chcl t (n + 1) - 29 ns iochrdy sampling start time t clr 0ns command signal - delay time from iochrdy - notes 1, 2 t rhch t m t (n + m) + 29 ns iochrdy hold time (from command signal - ) note 1 t chrl 0ns data output setup time (to command signal ) note 1 t dvcl - 15 ns data output hold time (from command signal - ) note 1 t chdv 25 ns memcs16#/iocs16# sampling start time note 2 t avsv1 2 t n C 44 ns memcs16#/iocs16# hold time (from command signal - ) note 1 t chsv 0ns data input setup time t ds 0ns data input hold time t dh 15 ns notes 1. with the v r 4111, the memw# and memr# signals are called the command signals for the high-speed system bus interface. 2. the values of n and m are set by using the wlcd/m (0:2) bits of the bcuspeedreg register. the value of t is set by using the clksel (0:2) bits (txd/clksel2, rts#/clksel1, and dtr#/clksel0). clksel2 clksel1 clksel0 t (ns) wlcd/m2 wlcd/m1 wlcd/m0 n (tclock) m (tclock) 1 note 1 note 1 note rfu 00088 1 note 1 note 0 note rfu 00177 1 note 0 note 1 note rfu 01066 1 note 0 note 0 note rfu 01155 0 1 1 43.3 1 0 0 4 4 0 1 0 45.9 1 0 1 3 3 0 0 1 48.4 1 1 0 2 2 0 0 0 40.7 1 1 1 1 2 note do not set clksel2 to 1.
data sheet u13211ej2v0ds00 115 m m m m pd30111 (14) high-speed system bus parameter (iochrdy) (2/2) remark the broken lines indicate high impedance. t avcl t clch t chcl t rhch t chrl t chdv t chav invalid invalid hi-z invalid t dh t ds t dvcl t clr add (19:25), add (0:8) (output) add (9:18) (output) shb# (output) lcdcs# (output) memr#/memw# (output) iochrdy (input) zws# (input) data (output) data (input) when wisaa (2:0) = 111 memcs16#, iocs16# (input) t chsv t avsv1
data sheet u13211ej2v0ds00 116 m m m m pd30111 (15) high-speed system bus parameter (zws#) (1/2) parameter symbol condition min. max. unit address setup time (to command signal ) notes 1, 2 t avcl t n - 29 ns command signal low-level width notes 1, 2 t clch t n - 31 ns address hold time (from command signal - ) note 1 t chav 25 ns command signal recovery time notes 1, 2 t chcl t (n + 1) - 29 ns zws# delay time from command signal notes 1, 2 t clzl t (n - 1) - 20 ns zws# signal hold time (from command signal - ) note 1 t chzh 0ns data output setup time (to command signal ) note 1 t dvcl - 15 ns data output hold time (from command signal - ) note 1 t chdv 25 ns memcs16#/iocs16# sampling start time note 2 t avsv2 2 t (n C 1) C 44 ns memcs16#/iocs16# hold time (from command signal - ) note 1 t chsv 0ns data input setup time t ds 0ns data input hold time t dh 15 ns notes 1. with the v r 4111, the memw# and memr# signals are called the command signals for the high-speed system bus interface. 2. the value of n is set by using the wisaa (0:2) bits of the bcuspeedreg register. the value of t is set by using the clksel (0:2) bits (txd/clksel2, rts#/clksel1, and dtr#/clksel0). clksel2 clksel1 clksel0 t (ns) wisaa2 wisaa1 wisaa0 n (tclock) 1 note 1 note 1 note rfu 0008 1 note 1 note 0 note rfu 0017 1 note 0 note 1 note rfu 0106 1 note 0 note 0 note rfu 0115 01143.3 1004 01045.9 1013 00148.4 1102 00040.7 1111 note do not set clksel2 to 1.
data sheet u13211ej2v0ds00 117 m m m m pd30111 (15) high-speed system bus parameter (zws#) (2/2) remark the broken lines indicate high impedance. t chcl add (19:25), add (0:8) (output) add (9:18) (output) shb# (output) lcdcs# (output) memr#/memw# (output) iochrdy (input) zws# (input) data (output) data (input) invalid invalid invalid t dh t ds t chav t clch t avcl t clzl t chzh t chdv hi-z t dvcl when wisaa (0:2) = 111 memcs16#, iocs16# (input) t chsv t avsv2
data sheet u13211ej2v0ds00 118 m m m m pd30111 (16) lcd interface parameter (1/2) parameter symbol condition min. max. unit address setup time (to command signal ) note 1 t as 15 ns address hold time (from command signal - ) note 1 t ah 0ns command signal recovery time note 1 t ry 30 ns lcdrdy sampling start time t clr 0ns command signal delay time from lcdrdy - notes 1, 2 t rhch t nt (n + 2) + 29 ns lcdrdy hold time (from command signal - ) note 1 t ryz 0ns data output setup time (to command signal - ) notes 1, 2 t dvch t (n + 2) ns data output hold time (from command signal - ) note 1 t chdv 25 ns data input setup time (to command signal - ) note 1 t ds 0ns data input hold time (from command signal - ) note 1 t dh 15 ns notes 1. with the v r 4111, the rd# and wr# signals are called the command signals for the lcd interface. 2. the values of n is set by using the wlcd/m (0:1) bits of the bcuspeedreg register. the value of t is set by using the clksel (0:2) bits (txd/clksel2, rts#/clksel1, and dtr#/clksel0). clksel2 clksel1 clksel0 t (ns) wlcd/m1 wlcd/m0 n (tclock) 1 note 1 note 1 note rfu 008 1 note 1 note 0 note rfu 016 1 note 0 note 1 note rfu 104 1 note 0 note 0 note rfu 112 0 1 1 43.3 0 1 0 45.9 0 0 1 48.4 0 0 0 40.7 note do not set clksel2 to 1.
data sheet u13211ej2v0ds00 119 m m m m pd30111 (16) lcd interface parameter (2/2) remark the broken lines indicate high impedance. shb# (output) lcdcs# (output) rd#/wr# (output) add (19:20), add (0:8) (output) add (9:18) (output) t ah invalid t as lcdrdy (input) data (output) data (input) invalid invalid t clr t rhch t dvch t chdv t ry t ryz t ds t dh hi-z
data sheet u13211ej2v0ds00 120 m m m m pd30111 (17) bus hold parameter (1/2) parameter symbol condition min. max. unit hldrq# input pulse width note t fhp in full-speed/standby mode 5t ns data floating delay time t foff in full-speed/standby mode 0 ns data valid delay time t fon in full-speed/standby mode 0 ns hldrq# input pulse width note t shp in suspend mode 12t ns data floating delay time t soff in suspend mode 0 ns data valid delay time t son in suspend mode 0 ns mras (0:3)# precharge time t rps in suspend mode 110 ns ucas#/lcas# setup time t csr in suspend mode 5 ns note the value of t is set by using the clksel (0:2) bits (txd/clksel2, rts#/clksel1, and dtr#/clksel0). clksel2 clksel1 clksel0 t (ns) 1 note 1 note 1 note rfu 1 note 1 note 0 note rfu 1 note 0 note 1 note rfu 1 note 0 note 0 note rfu 0 1 1 43.3 0 1 0 45.9 0 0 1 48.4 0 0 0 40.7 note do not set clksel2 to 1.
data sheet u13211ej2v0ds00 121 m m m m pd30111 (17) bus hold parameter (2/2) (a) bus hold in fullspeed/standby mode notes 1. uucas#/mras3#, ulcas#/mras#2, mras (0:1)#, ucas#, lcas# 2. shb#, ior#, iow#, memr#, memw#, rd#, wr#, add (0:25), data (0:15), data (16:31)/gpio (16:31) (in 32-bit data bus mode) remark the broken lines indicate high impedance. (b) bus hold in suspend mode notes 1. in 32-bit mode: mras (0:1)# in 16-bit mode: uucas#/mras3#, ulcas#/mras2#, mras (0:1)# 2. in 32-bit mode: uucas#/mras3#, ulcas#/mras2#, ucas#, lcas# in 16-bit mode: ucas#, lcas# 3. shb#, ior#, iow#, memr#, memw#, rd#, wr#, add (0:25), data (0:15), data (16:31)/gpio (16:31) (in 32-bit data bus mode) remark the broken lines indicate high impedance. hi-z t fhp hi-z hldrq# (input) hldack# (output) note 1 note 2 busclk (output) t foff t fon hi-z t shp hi-z hldrq# (input) hldack# (output) note 1 note 3 busclk (output) hi-z t rps t soff t csr t rps t soff note 2 h
data sheet u13211ej2v0ds00 122 m m m m pd30111 (18) keyboard interface parameter (1/2) parameter symbol condition min. max. unit kscan (0:11) high-level width t scan 30 (k + 2) C 1 30.16 (k + 2) + 1 m s idle time (kscan (n+1) - from kscann )t kwait 30 (l + 1) C 1 30.16 (l + 1) + 1 m s key scan interval time t ki 30m C 1 30.16m + 1 m s key input setup time (to kscann - )t ks 30 (n + 1) C 1 m s key input hold time (from kscann - )t kh 0 m s notes 1. k: sum of the values set to the t1cnt (0:4) bits and t2cnt (0:4) bits of the kiuwks register 2. l: value set to the t3cnt (0:4) bits of the kiuwks register 3. m: value set to kiuwki register 4. n: value set to the t1cnt (0:4) bits of the kiuwks register 5. n = 0 to 11 (a) keyboard scan parameter 1 remark n = 0 to 10 (b) keyboard scan parameter 2 hi-z hi-z hi-z t scan t kwait kscann (output) kscan (n + 1) (output) hi-z t kwait kscan0 (output) kscan11 (output) hi-z hi-z hi-z hi-z hi-z kscan1 (output) kscan2 (output) hi-z hi-z t kwait + t ki t kwait
data sheet u13211ej2v0ds00 123 m m m m pd30111 (18) keyboard interface parameter (2/2) (c) keyboard port parameter remark n = 0 to 11 hi-z t ks kscann (output) kport (0:7) (input) hi-z t kh
data sheet u13211ej2v0ds00 124 m m m m pd30111 (19) serial interface parameter (1/2) parameter symbol condition min. max. unit txd output pulse width note t txd n C 1 n + 1 m s rxd input pulse width note t rxd (9/16) n m s irdout# high-level output pulse width note t irdout (3/16) n C 1 (3/16) n + 1 m s irdin input pulse width t irdin 1 m s note n: data transfer rate per bit, which is determined by the divisor of the baud-rate generator that is set with the siudll and siudlm registers. baud rate (bps) siudlm, siudll n ( m s) 50 23,040 20,000 75 15,360 13,333 110 10,473 9,091 134.5 8,565 7,435 150 7,680 6,667 300 3,840 3,333 600 1,920 1,667 1,200 920 833 1,800 640 556 2,000 573 500 2,400 480 417 3,600 320 278 4,800 240 208 7,200 160 139 9,600 120 104 19,200 60 52.1 38,400 30 26.0 56,000 21 17.9 128,000 9 7.81 144,000 8 6.94 192,000 6 5.21 230,400 5 4.34 288,000 4 3.47 384,000 3 2.60 576,000 2 1.74 1,152,000 1 0.868
data sheet u13211ej2v0ds00 125 m m m m pd30111 (19) serial interface parameter (2/2) txd (output) t txd rxd (input) irdout# (output) irdin (input) t rxd t irdout t irdin
data sheet u13211ej2v0ds00 126 m m m m pd30111 (20) debug serial interface parameter parameter symbol condition min. max. unit ddout output pulse width note t ddout n C 1 n + 1 m s ddin input pulse width note t ddin (9/16) n m s note n: transfer rate of baud rate per bit set to the bpr0 bits of the bprm0reg register. bpr0 (2:0) baud rate (bps) n ( m s) 111 115,200 8.68 110 57,600 17.36 101 38,400 26.04 100 19,200 52.03 011 9,600 104.16 010 4,800 208.33 001 2,400 416.66 000 1,200 833.33 (21) hsp interface parameter parameter symbol condition min. max. unit sdo output delay time note 1 t sdod 15 ns sdi setup time note 2 t sdis 25 ns sdi hold time note 2 t sdih 0ns fs setup time note 2 t fsis 20 ns fs hold time note 2 t fsih 0ns notes 1. the reference clock of this parameter is the rising edge of hspsclk. 2. the reference clock of this parameter is the falling edge of hspsclk. ddin (input) ddout (output) t ddin t ddout
data sheet u13211ej2v0ds00 127 m m m m pd30111 a/d converter characteristics (t a = C 10 to +70 c, v dd2 = 2.3 to 2.7 v, v dd3 = 3.0 to 3.6 v) parameter symbol condition min. max. unit resolution 10 bit zero-scale error notes 1, 2 zse 0 4.0 lsb full-scale error notes 1, 2 rse 0 5.0 lsb integral linearity error notes 1, 2 inl 0 3.0 lsb differential linearity error notes 1, 2 dnl 0 3.0 lsb analog input voltage notes 1, 3 vian C0.3 av dd + 0.3 v notes 1. applied to tpx (0:1), tpy (0:1), adin (0:2), and audioin pins. 2. quantization error is excluded. 3. av dd is a voltage on the av dd pin that is v dd dedicated to the a/d converter. d/a converter characteristics (t a = C 10 to +70 c, v dd2 = 2.3 to 2.7 v, v dd3 = 3.0 to 3.6 v) parameter symbol condition min. max. unit resolution 10 bit integral linearity error notes 1, 2 inl 0 3.0 lsb differential linearity error notes 1, 2 dnl 0 3.0 lsb notes 1. applied to audioout pin. 2. quantization error is excluded. load coefficient (delay time per load capacitance) rating unit parameter symbol condition min. max. load coefficient cld 5 ns/20 pf
data sheet u13211ej2v0ds00 128 m m m m pd30111 24. package drawing s item millimeters inches b c d e g h 15.4 1.20 15.4 l 0.08 0.36 0.35 0.1 m c1.0 16.00 0.10 p 0.606 0.630 0.004 0.047 0.014 0.014 0.003 c0.039 0.606 + 0.004 - 0.005 224-pin fine pitch bga (16x16) a 16.00 0.10 0.630 0.004 f 0.8 (t.p.) i 0.96 0.038 j k 0.10 1.31 0.15 0.052 0.004 + 0.006 - 0.007 q r25 ? r0.3 r0.012 25 ? w 0.20 0.008 0.031 notes 1. controlling dimension millimeter. 2. each ball centerline is located within 0.08 mm of its true position (t.p.) at maximum material condition. f s sab a s b vutrpnmlk jhgfedcba f m b s a s c a b q h k m l p index mark j i g e f w d r w 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 y1 s224s1-3c-1 y1 0.20 0.008 0.50 + 0.05 - 0.10 0.020 + 0.002 - 0.005 ff
data sheet u13211ej2v0ds00 129 m m m m pd30111 25. recommended solering conditions the m pd30111 should be soldered and mounted under the following recommended conditions. for details of recommended soldering conditions, refer to the document semiconductor device mounting technology manual (c10535e) . for soldering methods and conditions other than those recommended below, contact your nec sales representative. table 25-1. surface mounting type soldering conditions soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 230 c, time: 30 seconds max. (at 210 c or higher), count: 2 times max., exposure limit: 3 days note (after that, prebake at 125 c for 10 to 72 hours.) ir30-103-2 vps package peak temperature: 215 c, time: 40 seconds max. (at 200 c or higher), count: 3 times max. , exposure limit: 3 days note (after that, prebake at 125 c for 10 to 72 hours.) vp15-103-2 partial heating pin temperature: 300 c max., time: 3 seconds max. (per pin row) ? note after opening the dry pack, store it at 25c or less and 65% rh or less for the allowable storage period. caution do not use different soldering methods together (except for partial heating).
data sheet u13211ej2v0ds00 130 m m m m pd30111 appendix differences between v r 4111 and v r 4102 item v r 4111 v r 4102 size instruction: 16 kbytes, data: 8 kbytes instruction: 4 kbytes, data: 1 kbyte cache memory parity check none provided instruction set mips iii + high-speed sum-of-products operation + mips16 mips iii + high-speed sum-of-products operation lcd interface bus width 16 bits, 32 bits 16 bits maximum dram capacity (edo type) 64 mbytes 32 mbytes memory controller maximum rom capacity 64 mbytes 32 mbytes power-on factor 4 types, 12 sources 4 types, 8 sources pull-up/pull-down of gpio (0:14) pins internal. can be independently set by means of software. external processing modem interface transmit/receive fifo: 96 bytes transmit/receive fifo: 32 bytes internal maximum operating frequency 70 mhz 49 mhz supply voltage internal: 2.5 v external: 3.3 v 3.3 v package 224-pin fbga 216-pin lqfp 224-pin fbga
data sheet u13211ej2v0ds00 131 m m m m pd30111 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
data sheet u13211ej2v0ds00 132 m m m m pd30111 [memo]
data sheet u13211ej2v0ds00 133 m m m m pd30111 regional information some information contained in this document may vary from country to country. before using any nec product in your application, piease contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. nec electronics inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 fax: 408-588-6130 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.l. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. velizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 nec electronics (france) s.a. spain office madrid, spain tel: 91-504-2787 fax: 91-504-2860 nec electronics (germany) gmbh scandinavia office taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. united square, singapore 1130 tel: 65-253-8311 fax: 65-250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-2719-2377 fax: 02-2719-5951 nec do brasil s.a. electron devices division rodovia presidente dutra, km 214 07210-902-guarulhos-sp brasil tel: 55-11-6465-6810 fax: 55-11-6465-6829 j99.1
m m m m pd30111 related documents v r 4111 users manual (u13137e) v r 4102 users manual (u12739e) m pd30102 (v r 4102) data sheet (u12543e) reference document electrical characteristics for microcomputer (iei-601) note note this document number is that of the japanese version. the documents indicated in this publication may include preliminary versions. however, preliminary versions are not marked as such. v r 4000, v r 4100, v r 4102, v r 4110, v r 4111, v r 4300, v r 4400, and v r series are trademarks of nec corporation. mips is a trademark of mips technologies, inc. exporting this product or equipment that includes this product may require a governmental license from the u.s.a. for some countries because this product utilizes technologies limited by the export control regulations of the u.s.a. the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. nec corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. m7 98. 8

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